Gorabal A, D K N. FPGA Implementation of UART with Single Error Correction and Double Error Detection (UART-SEC-DED). IJET [Internet]. 2018 Jul. 20 [cited 2024 Jul. 27];7(3.12):23-7. Available from: https://www.sciencepubco.com/index.php/ijet/article/view/15856