FPGA Implementation of UART with Single Error Correction and Double Error Detection (UART-SEC-DED)
Keywords:AES, ASIC, Data security, GPP, VLIW architecture.
The Universal Asynchronous Receiver Transmitter (UART) is the very simple and significant sequential communication protocol which is basically utilized for microprocessors & microcontroller systems. It is a shorter range communication protocol, which able to perform half-duplex and full-duplex type of communication at baud rates. Though, UART is a type of shorter range communication still they are not resistant to noisy channel which leads to communication errors by flipping or loosing of bits. These kinds of signal errors are named as forward-errors. The correction of forward errors is a mechanism to handle and rectify those errors (i.e. Burst errors and Random bits error). Thus in this methodology, have introduced a UART-SEC-DED communication module design which utilizes the Hamming encoder and decoders to achieve the forward error correction. Finally, the proposed system will simulated and implemented on FPGA board and experimental outcomes shows the better efficiency in single error correction and detection of double errors.
 SzabÃ³, Roland, and Aurel Gontean. "The development process of an UART chip on FPGA for driving embedded devices." Design and Technology in Electronic Packaging (SIITME), 2015 IEEE 21st International Symposium for. IEEE, 2015.
 Yamuna, T., and M. M. Dasu. "Systemverilog Implementation of UART with Single Error Correction and Double Error Detection", 2016
 Chun-Zhi, He, Xia Yin-shui, and Wang Lun-yao. "A universal asynchronous receiver transmitter design." Electronics, Communications and Control (ICECC), 2011 International Conference on. IEEE, 2011.
 Deepika S S, Ashwin Kumar, Nisha "A VHDL implementation of UART design with Error Coding Algorithms" IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278-2834,p- ISSN: 2278-8735.Volume 12, Issue 4, Ver. II (Jul.-Aug. 2017), PP 69-73.
 Muppalla, Sindhuaja, and Koteswara Rao Vaddempudi. "Signal Processing And Communication Engineering Systems (SPACES), 2015 International Conference on. IEEE, 2015.
 Patel, Naresh, Vatsalkumar Patel, and Vikaskumar Patel. "VHDL implementation of UART with status register." Communication Systems and Network Technologies (CSNT), 2012 International Conference on. IEEE, 2012.
 Norhuzaimin, J., and H. H. Maimun. "The design of high speed UART." Applied Electromagnetics, 2005. APACE 2005. Asia-Pacific Conference on. IEEE, 2005.
 Patel, Himanshu, et al. "A robust UART architecture based on recursive running sum filter for better noise performance " VLSI Design, 2007. Held Jointly with 6th International Conference on Embedded Systems., 20th International Conference on. IEEE, 2007.
 Fang, Yi-yuan, and Xue-jun Chen. "Design and simulation of UART serial communication module based on VHDL." Intelligent Systems and Applications (ISA), 2011 3rd International Workshop on. IEEE, 2011
 Idris, Mohd Yamani Idna, and Mashkuri Yaacob. "A VHDL implementation of BIST technique in UART design." TENCon 2003. Conference on Convergent Technologies for the Asia-Pacific Region. Vol. 4. IEEE, 2003
 Idris, Mohd Yamani Idna, Mashkuri Yaacob, and Zaidi Razak. "A VHDL implementation of UART design with BIST capability." Malaysian Journal of Computer Science 19.1 (2006): 73-86
 Malviya, Abhay, and Vijay Kumar Sharma. "An Improved Approach of UART Implementation in VHDL using Status Register." IJDACR, 2016
 Ashwini, Bennuri, Payata Srikanth Yadav, and T. Ashok Kumar Reddy. "Implementation of Universal Asynchronous Receiver and Transmitter." Research Arcticle, 2015
 Bhadra, Dipanjan, Vikas S. Vij, and Kenneth S. Stevens. "A low power UART design based on asynchronous techniques." Circuits and Systems (MWSCAS), IEEE 56th International Midwest Symposium on. IEEE, 2013.
View Full Article:
How to Cite
LicenseAuthors who publish with this journal agree to the following terms:
- Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under aÂ Creative Commons Attribution Licensethat allows others to share the work with an acknowledgement of the work''s authorship and initial publication in this journal.
- Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal''s published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
- Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (SeeÂ The Effect of Open Access).