Noorbasha F, Hari Kishore K, Phani Sarad P, Renuka A, Meera Mohiddin S, Jagadeesh Babu K, et al. A VLSI implementation of train collision avoidance system using Verilog HDL. IJET [Internet]. 2018 Mar. 19 [cited 2024 May 2];7(2.8):386-91. Available from: https://www.sciencepubco.com/index.php/ijet/article/view/10468