A VLSI implementation of train collision avoidance system using Verilog HDL

Now a days we see many train accidents that occur in railways. These accidents occur mainly due to cracks in the track, human errors and not identifying the opposite train at the right time. When the train meets with the accident lot of people lose their lives and huge amount of railway property is destroyed and it also takes lot of time to hold back to the normal situations. Most of the accidents happen due to human error and due to lack of communication between the trains and irregularity of Train Traffic Control System. Normally to prevent these accidents we place sensors on either side of the platform to identify the train at right time and to receive traffic signals at the platform properly. Here we came with some different approach which is easy to manage and implement and cost effective. Normally collision occurs when two trains approaching in opposite directions on same track. So, if we manage to prevent two trains travel on the same track then collision can be avoided. Here in this project we have implemented Verilog code to solve this problem. The purpose of this project is to write a Verilog code to detect the opposite train and deviate the train based on priority of the trains thus avoiding collision. In this project we have chosen four different types of trains namely Goods, Passenger, Superfast, Express and we have implemented train collision avoidance using Verilog code by giving priority to each type of train and preference is given to one train to avoid collision.