GORABAL, Amrutha; D K, Nayana. FPGA Implementation of UART with Single Error Correction and Double Error Detection (UART-SEC-DED). International Journal of Engineering & Technology, [S. l.], v. 7, n. 3.12, p. 23–27, 2018. DOI: 10.14419/ijet.v7i3.12.15856. Disponível em: https://www.sciencepubco.com/index.php/ijet/article/view/15856.. Acesso em: 25 may. 2024.