NOORBASHA, Fazal; HARI KISHORE, K; PHANI SARAD, P; RENUKA, A; MEERA MOHIDDIN, SK; JAGADEESH BABU, K; V S. PHANINDRA, B; MANASA, M. A VLSI implementation of train collision avoidance system using Verilog HDL. International Journal of Engineering & Technology, [S. l.], v. 7, n. 2.8, p. 386–391, 2018. DOI: 10.14419/ijet.v7i2.8.10468. Disponível em: https://www.sciencepubco.com/index.php/ijet/article/view/10468.. Acesso em: 2 may. 2024.