Implementation of logic gates using CNFET for energy constraint applications

  • Abstract
  • Keywords
  • References
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  • Abstract

    Since the advent of semiconductors and throughout the history of designing ICs in VLSI for everything from computer hardware to mobile phones, the basic principle of Moore's law has persisted to be the same the number of transistors on a given area of silicon doubles every two years. The transistor rely on today's propelled multicore processors will be arriving at those extent about three billions, a in length best approach starting with the 6800 processor of the mid 1970s which comprised of Exactly 5000 transistors. Semiconductor manufacturing commercial enterprises need aid supporting of the most extreme degree to make this Growth feasible by presenting scaled CMOS gadgets utilizing field impact transistor (FET) technology, the place the most recent hub adequately multiplied those entryway thickness contrasted with those past era each few for A long time. As the approach will be crashing towards sub-nano meter reach that is past 90-nm node, spillage turned into a paramount element. Same time those MOS gadgets arrived at the end of its versatile limit, those semiconductor industry found elective gadget for example, such that CNFET (carbon nano tube field impact transistor), which will be acknowledged to the best decision for following era units. Large portions semiconductor commercial enterprises need aid placing their deliberations On CNFET innovation.


  • Keywords

    Logic Gates; Ultra-Low Power; Performance; CNTFET; and MOSFET.

  • References

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Article ID: 9852
DOI: 10.14419/ijet.v7i1.1.9852

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