Design of low power 10GS/s 6-Bit DAC using CMOS technology

  • Authors

    • P. Ramakrishna
    • K Hari Kishore
    2017-12-31
    https://doi.org/10.14419/ijet.v7i1.5.9151
  • R_2R ladder network, high-speed logic, current steering DAC, DTMOS, CMOS technology.

  • A Low power 6-bit R-2R ladder Digital to Analog Converter is presented in this paper. Here the    R-2 R network designed using resistors with only two values-R and 2xRand the switch is designed by using both NMOS and PMOS Transistors. This Digital to Analog Converters operated with low voltage, by applying dynamic threshold MOSFET (DTMOS) logic. This design achieved less INL and DNL which is 0.3 and 0.06 respectively. Power supply required to operate this device is only 1V with10GHzconversion rate. This design is implemented by using 0.18μm CMOS technology.

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    Ramakrishna, P., & Hari Kishore, K. (2017). Design of low power 10GS/s 6-Bit DAC using CMOS technology. International Journal of Engineering & Technology, 7(1.5), 226-229. https://doi.org/10.14419/ijet.v7i1.5.9151