VLSI design for efficient RSD-Based ECC processor using Karatsuba algorithm

 
 
 
  • Abstract
  • Keywords
  • References
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  • Abstract


    In this paper, an exportable application-particular direction set elliptic bend cryptography processor in view of repetitive marked digit portrayal is proposed. The processor utilizes broad pipelining strategies for Karatsuba– Of man strategy to accomplish high throughput augmentation. Moreover, an effective particular viper without correlation and a high throughput measured divider, which brings about a short data path for expanded recurrence, are actualized. The proposed design of this paper investigation the rationale size, region and power utilization utilizing Xilinx 13.2. The expansion for the task is Vedic Sutra – Nikhilam Sutra.


  • Keywords


    Application Specific Instruction-set Processor (ASIP), Elliptic Curve Cryptography (ECC), Field Programmable Gate Array (FPGA), Karatsuba–Ofman Multiplication, Redundant Signed Digit (RSD).

  • References


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Article ID: 9140
 
DOI: 10.14419/ijet.v7i1.5.9140




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