Implementation of FPGA based MRPMA for high performance applications

 
 
 
  • Abstract
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  • References
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  • Abstract


    In the last few decay, Network on Chip’s (NoC) are the powerful chips for high speed communications pertaining to 802.11 Ethernet protocol which is a need to be reconfigurable for successful data frame transmission. The existing architectures like coarse grained reconfigurable, ALU cluster and expression grain reconfigurable architecture and look-up-table used in fine grained reconfigurable devices requires a lot of storage memory, hardware resources such as slices, cell area and cell delay. To tackle these issues, Multigrained Reconfiguration and Parallel Mapping Architecture (MRPMA) is proposed and their performance analysis parameters are calculated. The MRPMA uses the four contributions to optimize Processing Elements (PE’s) operations: 1) Fast Fourier Transformation (FFT) to perform fixed point numbers to the configuration words, 2) Discrete Cosine Transformation (DCT) to analyze the data in the frequency domain, 3) Finite Impulse Response (FIR) for parallel mapping the data and 4) Channel encoder and decoder to encode the data and to calculate the shortest route from source to destination switch.   


  • Keywords


    FFT, DCT, FIR, Channel encoder, FPGA, MRPMA, NoC.

  • References


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Article ID: 9139
 
DOI: 10.14419/ijet.v7i1.5.9139




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