Low-power, low-latency transceiver design using d-TGMS flip-flop for on-chip interconnects

Authors

  • U. Saravanakumar Department of ECE,Veltech Dr. RR & Dr. SR University,Avadi, Chennai
  • P Suresh Department of ECE,Veltech Dr. RR & Dr. SR University,Avadi, Chennai
  • S.P Vimal Department of ECE, Sri Ramakrishna Engg. College, Coimbatore

DOI:

https://doi.org/10.14419/ijet.v7i1.8730

Published:

2018-01-29

Keywords:

Network on Chip, Serialiser-Deserialiser, On-Chip Interconnects, D-TGMS, Low Power.

Abstract

The routers in Network on Chips (NoCs) are used to transmit the data among the Processing Elements (PEs) in the field, and it can be done through transmission links between the routers. Traditionally, the data transmission between the PEs of NoC is carried out by the parallel bus which consumes more power, leads to be complex routing strategies and occupies more area within the field. Instead of parallel bus, serializes and deserialisers are used for serial data transmission, which consumes very less power and area than traditional method. To implement serialiser-deserialiser at the transceiver in the router for on chip communication, a three-level encoding technique is implemented in this design, which eliminates power hungry blocks in earlier works, such as Phase Locked Loops, Feed Forward Equalizers, Decision Feedback Equalizers and the repeaters along the transmission line. In this paper, a low-power transceiver is proposed using modified C2MOS flip flop and Dynamic TGMS flip flop circuits in order to minimize the delay. The power reduction of 35.683% and the delay reduction of 44.71% were achieved in the proposed transceiver than the NAND gate based D flip flop transceivers.

Author Biography

U. Saravanakumar, Department of ECE,Veltech Dr. RR & Dr. SR University,Avadi, Chennai

VLSI Design, System on Chip, Network on Chip, FPGA

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