Performance Analysis of FinFET based SRAM at Nano-scaled Technology nodes for Low Power High Speed IC Design

  • Authors

    • Karmjit Singh Sandha Thapar Institute of Engineering and Technology, Patiala
    • Simranjit Singh hapar Institute of Engineering and Technology, Patiala
    2019-06-30
    https://doi.org/10.14419/ijet.v7i4.29315
  • This paper presents performance analysis of FinFET based SRAM in terms of delay, power and power delay product (PDP) at nano-scaled technology nodes. SRAM is generally used as memories in low powered electronics gadgets. The majority of transistors of an integrated circuits (IC) are utilized as SRAM bit cells with the percentage die occupied by this type of memory approaching 85%-90% of the total area of an ICs. As the demand for the low power high-speed devices is rising, and the emergence of Internet of Thing (IoT) devices, the need for scaled down SRAM has become essential. Since SRAM is typically constructed from traditional CMOS devices, all of the issues associated with MOSFET scaling are valid for SRAM as well. The focus of the paper is to study 6T FinFET SRAM, and evaluate the different performance metrics such as delay, power dissipation and PDP at deep-submicron technology nodes. A standard 6T FinFET SRAM cells are realized using predictive technology models (PTM) for 20, 16, 14, 10 and 7nm technology nodes. The performances these SRAM cells are evaluated and results are compared for previously stated performance parameters. It is shown in the results that 7nm FinFET SRAM cells performs better at all aspects and followed by 10, 14, 16 and 20nm technology nodes.

  • References

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      [2] R. W. Mann et al., "Array Termination Impacts in Advanced SRAM," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2449-2457, Sept. 2017.

      [3] T. W. Oh, H. Jeong, K. Kang, J. Park, Y. Yang and S. O. Jung, "Power-Gated 9T SRAM Cell for Low-Energy Operation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 1183-1187, March 2017.

      [4] S. Kurude, S. Mittal and U. Ganguly, "Statistical Variability Analysis of SRAM Cell for Emerging Transistor Technologies," in IEEE Transactions on Electron Devices, vol. 63, no. 9, pp. 3514-3520, Sept. 2016.

      [5] AA. G. Akkala, R. Venkatesan, A. Raghunathan and K. Roy, "Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs," in IEEE Transactions on Electron Devices, vol. 63, no. 3, pp. 1034-1040, March 2016.

      [6] N. Agrawal, H. Liu, R. Arghavani, V. Narayanan and S. Datta, "Impact of Variation in Nanoscale Silicon and Non-Silicon FinFETs and Tunnel FETs on Device and SRAM Performance," in IEEE Transactions on Electron Devices, vol. 62, no. 6, pp. 1691-1697, June 2015.

      [7] Y. Yang, H. Jeong, S. C. Song, J. Wang, G. Yeap and S. O. Jung, "Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 7, pp. 1023-1032, July 2016.

      [8] D. Kraak , "Degradation analysis of high performance 14nm FinFET SRAM," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 201-206.

      [9] T. Song et al., "A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 198-200

      [10] M. N. Kishor and S. S. Narkhede, "Design of a ternary FinFET SRAM cell," 2016 Symposium on Colossal Data Analysis and Networking (CDAN), Indore, 2016, pp. 1-5.

      [11] Computer organization. (4th ed.). [S.l.]: McGraw-Hill. ISBN 0-07-114323-8.

      [12] International Technology Roadmap for Semiconductors (ITRS).

      [13] San Jose, CA: Semiconductor Industry Association, 2007.

      [14] B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M. R. Lin, “15 nm gate length planar CMOS transistor,†in IEDM Tech. Dig., 2001, pp. 937–939.

      [15] D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, “FinFET—A self-aligned double-gate MOSFET scalable to 20 nm,†IEEE Trans. Electron Devices, vol. 47, pp. 2320–2325, 2000.

      [16] J. Y. S. Balasubramanium, “Design of sub-50 nm FinFET based low power SRAMs,†Semiconductor Science Technology, vol. 23, p. 13, 2008.

      [17] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “A 3-GHz 70 MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply,†in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 474–476.

      [18] B. Raj, A. K. Saxena and S. Dasgupta, "Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect," in IEEE Circuits and Systems Magazine, vol. 11, no. 3, pp. 38-50, third quarter 2011.

      [19] Colinge, J. (2011). FinFETs and other multi-gate transistors. New York: Springer.

      [20] E. Chin, M. Dunga, and B. Nikolic, “Design trade-offs of a 6T FinFET SRAM cell in the presence of variations,†in Proc. IEEE Symp. VLSI Circuits, 2006, pp. 445–449.

      [21] F. Sheikh and V. Varadarajan, “The impact of device-width quantization on digital circuit design using FinFET structures,†in Proc. EE241 Spring, 2004, pp. 1–6.

      [22] P. T. Su, C. H. Jin, C. J. Dong, H. S. Yeon, P. Donggun, K. Kinam, E. Yoon, and L. J. Ho, “Characteristics of the full CMOS SRAM cell using body tied TG MOSFETs (bulk FinFETs),†IEEE Trans. Electron Devices, vol. 53, pp. 481–487, 2006.

      [23] K. Itoh, K. Sasaki, and Y. Nakagome, “Trends in low power RAM circuit technology,†in Proc. IEEE IEDM Tech. Dig., Apr. 1995, pp. 524–543.

      [24] L. Bagheriye, R. Saeidi and S. Toofan, "Low power and roboust FinFET SRAM cell using independent gate control," 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 49-52.

      [25] Rashmi, A. Kranti, and G. A. Armstrong, “6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: Impact of source/drain engineering and circuit topology,†Semiconductor Science Technology, p. 13, 2008.

      [26] A. J. Bhavnagarwala, T. Xinghai, and J. D. Meindl, “The impact of intrinsic device fl uctuations on CMOS SRAM cell stability,†IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658–665, Apr. 2001.

      [27] A. D. Yang and L. S. Kim, “A low-power SRAM using hierarchical bit line and local sense amplifiers,†IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1366–1376, 2005.

      [28] H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, “SRAM leakage suppression by minimizing standby supply voltage,†in Proc. 5th Int. Symp. Quality Electronic Design, 2004, pp. 55–60.

      [29] J. H. Choi, A. Bansal, M. Meterelliyoz, J. Murthy, and K. Roy, “Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits,†in IEEE Proc. Int. Conf . Computer Aided Design (ICCAD), Nov. 5–9, 2006, pp. 583–586.

      [30] T. Miwa, J. Yamada, and H. Koike, “A 512 Kbit low voltage NV-SRAM with the size of a conventional SRAM,†in Symp. VLSl Circuits Dig., 2000, pp. 129–132.

      [31] K. Itoh, K. Sasaki, and Y. Nakagome, “Trends in low power RAM circuit technology,†in Proc. IEEE IEDM Tech. Dig., Apr. 1995, pp. 524–543.

      [32] A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. D. Meyer, “Analysis of the parasitic S/D resistance in multiple-gate FET,†IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1132–1139, June 2005.

      [33] X. Zhang et al., "Analysis of 7/8-nm Bulk-Si FinFET Technologies for 6T-SRAM Scaling," in IEEE Transactions on Electron Devices, vol. 63, no. 4, pp. 1502-1507, April 2016.

      [34] Seevinck, E., List, F. J., and Lohstroh, J., “Statis-Noise Margin Analysis of MOS SRAM Cells,â€, IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October, 1987.

      References

      [1]

      Y. Yang, H. Jeong, S. C. Song, J. Wang, G. Yeap and S. O. Jung, "Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 7, pp. 1023-1032, July 2016.

      [2]

      R. W. Mann et al., "Array Termination Impacts in Advanced SRAM," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2449-2457, Sept. 2017.

      [3]

      T. W. Oh, H. Jeong, K. Kang, J. Park, Y. Yang and S. O. Jung, "Power-Gated 9T SRAM Cell for Low-Energy Operation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 1183-1187, March 2017.

      [4]

      S. Kurude, S. Mittal and U. Ganguly, "Statistical Variability Analysis of SRAM Cell for Emerging Transistor Technologies," in IEEE Transactions on Electron Devices, vol. 63, no. 9, pp. 3514-3520, Sept. 2016.

      [5]

      A. G. Akkala, R. Venkatesan, A. Raghunathan and K. Roy, "Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs," in IEEE Transactions on Electron Devices, vol. 63, no. 3, pp. 1034-1040, March 2016.

      [6]

      N. Agrawal, H. Liu, R. Arghavani, V. Narayanan and S. Datta, "Impact of Variation in Nanoscale Silicon and Non-Silicon FinFETs and Tunnel FETs on Device and SRAM Performance," in IEEE Transactions on Electron Devices, vol. 62, no. 6, pp. 1691-1697, June 2015.

      [7]

      Y. Yang, H. Jeong, S. C. Song, J. Wang, G. Yeap and S. O. Jung, "Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 7, pp. 1023-1032, July 2016.

      [8]

      D. Kraak et al., "Degradation analysis of high performance 14nm FinFET SRAM," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 201-206.

      [10]

      T. Song et al., "A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 198-200.

      [11]

      M. N. Kishor and S. S. Narkhede, "Design of a ternary FinFET SRAM cell," 2016 Symposium on Colossal Data Analysis and Networking (CDAN), Indore, 2016, pp. 1-5.

      [12]

      Computer organization. (4th ed.). [S.l.]: McGraw-Hill. ISBN 0-07-114323-8.

      [13]

      International Technology Roadmap for Semiconductors (ITRS). San Jose, CA: Semiconductor Industry Association, 2007.

      [14]

      B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M. R. Lin, “15 nm gate length planar CMOS transistor,†in IEDM Tech. Dig., 2001, pp. 937–939.

      [15]

      D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, “FinFET—A self-aligned double-gate MOSFET scalable to 20 nm,†IEEE Trans. Electron Devices, vol. 47, pp. 2320–2325, 2000.

      [16]

      J. Y. S. Balasubramanium, “Design of sub-50 nm FinFET based low power SRAMs,†Semiconductor Science Technology, vol. 23, p. 13, 2008.

      [17]

      K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “A 3-GHz 70 MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply,†in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 474–476.

      [18]

      B. Raj, A. K. Saxena and S. Dasgupta, "Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect," in IEEE Circuits and Systems Magazine, vol. 11, no. 3, pp. 38-50, thirdquarter 2011.

      [19]

      Colinge, J. (2011). FinFETs and other multi-gate transistors. New York: Springer.

      [20]

      E. Chin, M. Dunga, and B. Nikolic, “Design trade-offs of a 6T FinFET SRAM cell in the presence of variations,†in Proc. IEEE Symp. VLSI Circuits, 2006, pp. 445–449.

      [21]

      F. Sheikh and V. Varadarajan, “The impact of device-width quantization on digital circuit design using FinFET structures,†in Proc. EE241 Spring, 2004, pp. 1–6.

      [22]

      P. T. Su, C. H. Jin, C. J. Dong, H. S. Yeon, P. Donggun, K. Kinam, E. Yoon, and L. J. Ho, “Characteristics of the full CMOS SRAM cell using body tied TG MOSFETs (bulk FinFETs),†IEEE Trans. Electron Devices, vol. 53, pp. 481–487, 2006.

      [23]

      K. Itoh, K. Sasaki, and Y. Nakagome, “Trends in low power RAM circuit technology,†in Proc. IEEE IEDM Tech. Dig., Apr. 1995, pp. 524–543.

      [24]

      L. Bagheriye, R. Saeidi and S. Toofan, "Low power and roboust FinFET SRAM cell using independent gate control," 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 49-52.

      [25]

      Rashmi, A. Kranti, and G. A. Armstrong, “6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: Impact of source/drain engineering and circuit topology,†Semiconductor Science Technology, p. 13, 2008.

      [26]

      A. J. Bhavnagarwala, T. Xinghai, and J. D. Meindl, “The impact of intrinsic device fl uctuations on CMOS SRAM cell stability,†IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658–665, Apr. 2001.

      [27]

      B. D. Yang and L. S. Kim, “A low-power SRAM using hierarchical bit line and local sense amplifiers,†IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1366–1376, 2005.

      [28]

      H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, “SRAM leakage suppression by minimizing standby supply voltage,†in Proc. 5th Int. Symp. Quality Electronic Design, 2004, pp. 55–60.

      [29]

      J. H. Choi, A. Bansal, M. Meterelliyoz, J. Murthy, and K. Roy, “Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits,†in IEEE Proc. Int. Conf. Computer Aided Design (ICCAD), Nov. 5–9, 2006, pp. 583–586.

      [30]

      T. Miwa, J. Yamada, and H. Koike, “A 512 Kbit low voltage NV-SRAM with the size of a conventional SRAM,†in Symp. VLSl Circuits Dig., 2000, pp. 129–132.

      [31]

      K. Itoh, K. Sasaki, and Y. Nakagome, “Trends in low power RAM circuit technology,†in Proc. IEEE IEDM Tech. Dig., Apr. 1995, pp. 524–543.

      [32]

      A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. D. Meyer, “Analysis of the parasitic S/D resistance in multiple-gate FET,†IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1132–1139, June 2005.

      [33]

      X. Zhang et al., "Analysis of 7/8-nm Bulk-Si FinFET Technologies for 6T-SRAM Scaling," in IEEE Transactions on Electron Devices, vol. 63, no. 4, pp. 1502-1507, April 2016.

      [34]

      Seevinck, E., List, F. J., and Lohstroh, J., “Statis-Noise Margin Analysis of MOS SRAM Cells,â€, IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October, 1987.

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  • How to Cite

    Sandha, K. S., & Singh, S. (2019). Performance Analysis of FinFET based SRAM at Nano-scaled Technology nodes for Low Power High Speed IC Design. International Journal of Engineering & Technology, 7(4), 6597-6602. https://doi.org/10.14419/ijet.v7i4.29315