CTS-SRAM: Design of Low Power CMOS Transmission Gate and Sleep Transistor based SRAM Cell

 
 
 
  • Abstract
  • Keywords
  • References
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  • Abstract


    In modern technology era, the demand for Static Random Access Memory (SRAM) cells has been greatly increased due to its wide variety of applications. Power consumption, speed, read stability and leakage issues are the major design challenges related to SRAM. This paper presents a novel SRAM cell based on Multiple Supply Voltages and non-precharged RBL (MS-N10T) and also shows the comparison of various SRAM cells based on lector, sleep transistors and Transmission gate (TG) to reduce the power consumption when compared to LP10T. The SRAM cell MS-N10T when used in combination of TG and sleep transistors (TGNS-13T) further reduces the power consumption. The analysis further shows that the SRAM, TGNS13T reduces the power consumption approximately by 70-80%. On the Other hand, the LC14T SRAM cell enhances the stability approximately by 80-85%. The major objective of this work is to reduce the power consumption with marginal increase in propagation delay and to improve read stability so as to meet the challenges of advancements in technologies. All the various SRAM architectures are implemented using Cadence 45nm CMOS technology.

     

     

     


  • Keywords


    CTG-12T; LP10T; LC14T; MS-N10T; Precharge; TGS-14T and TGNS-13T.

  • References


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Article ID: 27960
 
DOI: 10.14419/ijet.v7i4.19.27960




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