CTS-SRAM: Design of Low Power CMOS Transmission Gate and Sleep Transistor based SRAM Cell

  • Abstract
  • Keywords
  • References
  • PDF
  • Abstract

    In modern technology era, the demand for Static Random Access Memory (SRAM) cells has been greatly increased due to its wide variety of applications. Power consumption, speed, read stability and leakage issues are the major design challenges related to SRAM. This paper presents a novel SRAM cell based on Multiple Supply Voltages and non-precharged RBL (MS-N10T) and also shows the comparison of various SRAM cells based on lector, sleep transistors and Transmission gate (TG) to reduce the power consumption when compared to LP10T. The SRAM cell MS-N10T when used in combination of TG and sleep transistors (TGNS-13T) further reduces the power consumption. The analysis further shows that the SRAM, TGNS13T reduces the power consumption approximately by 70-80%. On the Other hand, the LC14T SRAM cell enhances the stability approximately by 80-85%. The major objective of this work is to reduce the power consumption with marginal increase in propagation delay and to improve read stability so as to meet the challenges of advancements in technologies. All the various SRAM architectures are implemented using Cadence 45nm CMOS technology.




  • Keywords

    CTG-12T; LP10T; LC14T; MS-N10T; Precharge; TGS-14T and TGNS-13T.

  • References

      [1] Maisagalla Gopal and Balwinder Raj (2013), “Low power 8T SRAM cell design for high stability video applications,” ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE), Vol. 1.

      [2] L.Chang et al. (June 2005), “Stable SRAM cell design for the 32 nm node and beyond,” in Symposium on VLSI Technology Digest of Technical Papers, pp. 128-129.

      [3] B. Wang, T. Q. Nguyen, A. T. Do, J. Zhou, M. Je, and T. T. H. Kim (Feb. 2015), “Design of an ultra-low voltage 9T SRAM with equalized bitline leakage and CAM-assisted energy efficiency improvement,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 62, no. 2, pp. 441–448.

      [4] S. Lin, Y.-B. Kim and F. Lombardi (2008), “A low leakage 9t SRAM cell for ultra-low power operation,” in Proc. 18th ACM Great Lakes Symp. VLSI, pp. 123–126.

      [5] B. H. Calhoun and A. P. Chandrakasan (March 2007), “A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation,” IEEE J. Solid-State Circuits, Vol. 42, no. 3, pp. 680–688.

      [6] H. Noguchi et al. (June 2008), “Which is the best dual-port SRAM in 45-nm process technology?—8T, 10T single end, and 10T differential,” in Proc. IEEE Int. Conf. Integr. Circuit Design Technol. Tut, pp. 55–58.

      [7] Naeem Maroof and Bai-Sun Kong (April 2017) , “10T SRAM using half-vdd precharge and row-wise dynamically powered read port for low switching power and ultralow RBL leakage,” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 25.

      [8] Y. Alekhya , J. Sudhakar (March - April 2017), “Design of 64 bit SRAM using lector technique for low leakage power with read and write enable,” IOSR Journal of VLSI and Signal Processing (IOSR-JVSP),Vol. 7, pp. 10-19.

      [9] Joshika Sharma, Saurabh and Shyam Akashe (2015), “Implementation of high performance SRAM cell using transmission gate,” Fifth International Conference on Advanced Computing & Communication Technologies, pp. 257-260.

      [10] Katie Ann Blomster (August 2006), “Schemes for reducing power and delay in SRAMs”.




Article ID: 27960
DOI: 10.14419/ijet.v7i4.19.27960

Copyright © 2012-2015 Science Publishing Corporation Inc. All rights reserved.