Design and Implementation of High Speed and Low Power Factorial Circuit

This paper deals with design of factorial circuit which turns on only for valid inputs and thus reduce unwanted transitions in the parallel circuitry by switching off the unused multipliers for inputs less than the maximal. The inputs are fed to the multiplier circuit through tristate buffers and control signals are produced using decoder. This in turn minimizes the dynamic power dissipation and reduces delay. The experimental evaluation of the proposed factorial circuit is done using simulation outputs and by comparing the performance parameters with prior designs in terms of power dissipation and delay. The functionality of the proposed circuit is verified by implementing in a combination and permutation circuit.