An Improved Multiplication Algorithm

Authors

  • S. Subha
  • . .

DOI:

https://doi.org/10.14419/ijet.v7i4.10.26666

Published:

2018-10-02

Keywords:

multiplication, Binarynumberrepresentation, Lawofindices, Performance

Abstract

Multiplication is commonly used arithmetic operation in computers. An algorithm is proposed to perform multiplication of positive numbers using law of indices. The two inputs  A and B are represented as binary numbers. Iteratively, the number A is multiplied with the bits in B. The coefficients of the partial products are accumulated. These coefficients are represented as binary numbers, the result coefficients are calculated. The proposed algorithm is simulated using Quartus 2 tool for two four bit inputs. An improvement in timing by 18%  with comparable power consumption and increased area is observed for input of four bits. The proposed algorithm can be extended for n-bit inputs.

 

 

 

References

[1] Israel Koren(1993), Computer Arithmetic Algorithms, Prentice Hall, NJ

[2] Jongsu Park, San Kim, Yong-Surk Lee (2004), A Low-Power Booth Multiplier Using Novel Data Partition Method, Proceedings of AP-ASIC , pp. 54-57

[3] Nan-Ying Shen, OscalT.C. Chen (2002), Low Power Multipliers by Minimizing Switching Activities of Partial Products, Proceedings of ISCAS, pp. IV-93-IV-96

[4] Philip.E.Madrid, Brian Millar, Earl E Swartzlander Jr. (1993), Modified Booth Algorithm for High Radix Floating point Multiplication , IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 1, pp.164-167

[5] RajendraKatti (1994), A Modified Booth Algorithm for High Radix Fixed Point Multiplication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 2, pp, 522-524

[6] Sandy Wang, Yi-Wen Wu, OscalT.C.Chen, Ruey-Lian Ma (2000), Low Power Multipliers by Minimizing Inter-Data Switching Activities, Proceedings of IEEE Midwest Symposium on Circuits and Systems Vol. I, pp.89-92

[7] S Subha, R Sakthivel (2016) A Power Saving Multiplication Algorithm, IJAER, Vol. 11, pp. 6200-6203

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How to Cite

Subha, S., & ., . (2018). An Improved Multiplication Algorithm. International Journal of Engineering & Technology, 7(4.10), 1027–1028. https://doi.org/10.14419/ijet.v7i4.10.26666

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Received 2019-01-29
Accepted 2019-01-29
Published 2018-10-02