An Improved Multiplication Algorithm

  • Abstract
  • Keywords
  • References
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  • Abstract

    Multiplication is commonly used arithmetic operation in computers. An algorithm is proposed to perform multiplication of positive numbers using law of indices. The two inputs  A and B are represented as binary numbers. Iteratively, the number A is multiplied with the bits in B. The coefficients of the partial products are accumulated. These coefficients are represented as binary numbers, the result coefficients are calculated. The proposed algorithm is simulated using Quartus 2 tool for two four bit inputs. An improvement in timing by 18%  with comparable power consumption and increased area is observed for input of four bits. The proposed algorithm can be extended for n-bit inputs.




  • Keywords

    multiplication, Binarynumberrepresentation, Lawofindices, Performance

  • References

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      [4] Philip.E.Madrid, Brian Millar, Earl E Swartzlander Jr. (1993), Modified Booth Algorithm for High Radix Floating point Multiplication , IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 1, pp.164-167

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      [6] Sandy Wang, Yi-Wen Wu, OscalT.C.Chen, Ruey-Lian Ma (2000), Low Power Multipliers by Minimizing Inter-Data Switching Activities, Proceedings of IEEE Midwest Symposium on Circuits and Systems Vol. I, pp.89-92

      [7] S Subha, R Sakthivel (2016) A Power Saving Multiplication Algorithm, IJAER, Vol. 11, pp. 6200-6203




Article ID: 26666
DOI: 10.14419/ijet.v7i4.10.26666

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