Implementation of the Hard-Decision Low Density Parity Check Codes in A 0.13µm CMOS Process

  • Authors

    • Daryl P. Pongcol
    • Roberto B. Madronial Jr.
    • Olga Joy L. Gerasta
    • Jefferson A. Hora
    • J. Banuchandar
    2018-11-30
    https://doi.org/10.14419/ijet.v7i4.28.25390
  • Decoder, Error correcting code (ECC), Low density parity check (LDPC), Parity check
  • This paper presents a simple and efficient implementation of a Low Density Parity Check (LDPC) error-correcting code, using the hard-decision decoding algorithm in a 0.13 µm TSMC CMOS process. The encoder and decoder modules were simulated by transmitting the correct 8bit code words, and letting it pass through a test bench module that corrupts one or more bits of the channel data, then allowing the decoder to correct the corrupted channel data. The system is able to correct a single bit error with 1 or 2 iterations only. Hence for a clock of 50MHz, the system can detect and correct more than 42 bit errors per 1 KB of data, which is just the goal of this research. Implemented through Verilog HDL using Synopsys Design, the design is simple in a sense that it does not use sophisticated encoding and decoding algorithms and the H- matrix used is a simple ½ code rate (4,8)- regular matrix and thus will result to a small scale and non-congested full-parallel architecture. It only measured 6.29 mm2 chip area. For a supply voltage of 1.32 V, the total power of only 138.64 µW implied very low power consumption.

     

     

  • References

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  • How to Cite

    P. Pongcol, D., B. Madronial Jr., R., Joy L. Gerasta, O., A. Hora, J., & Banuchandar, J. (2018). Implementation of the Hard-Decision Low Density Parity Check Codes in A 0.13µm CMOS Process. International Journal of Engineering & Technology, 7(4.28), 577-581. https://doi.org/10.14419/ijet.v7i4.28.25390