Investigation of 6T SRAM Characteristics Using TFET
Keywords:Buffer, CMOS, Hetero junction, SRAM read/write, SRAM, TFET.
This paper proposes to design and investigate the SRAM memory cell features using TFET in the InAs/GaSb-InAs platform. This platform lies within the type III (Hetero-junction) alignment in TFET. The word TFET symbolizes to the Tunneling Field Effect Transistor which is related to the MOSFET but follows quantum tunneling switching mechanism. TFET having an advantage over MOSFET such as high speed, energy efficient and low power applications in the field of integrated circuits. The suggested project is the design of 6T SRAM memory cell with 32nm TFET technology. Finally, the performance estimation of the proposed SRAM has been compared with CMOS, FinFET, and CNFET. The study of the competence of the SRAM cell can be done by Hspice tool and Verilog-A language used.
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