Design a Glitch Tolerant Adiabatic Dynamic Logic Circuits for Cryptography

  • Authors

    • A. Naga Ganesh
    • Michael Cholines Pedapudi
    • N. V. Apparao
    • . .
    2018-11-27
    https://doi.org/10.14419/ijet.v7i4.19.23173
  • Parallel Prefix Adder, Ripple carry adder, carry save adder (CSA), Field-Programmable-Gate-Array (F.P.G.A), Digital Signal Processing (DSP), Look Up Table (LUT).
  • Adiabatic logic design is an efficient superconductor logic which performs adiabatic switching operation. The Adiabatic logic is the most essential part of the variable latency design.  The design of conventional CMOS logic circuit depends on the charging of output capacitive nodes. Here a glitch tolerant adiabatic design logic is proposed. For stumpy power applications, although there are many ‘techniques’ mutually at way level and system stage. To reduce the power consumption, the charging of capacitive nodes should process the operating part in slow manner.  From this it can observe that it takes less amount of energy to charge the capacitive nodes. Several Adiabatic designs have been proposed in literature. Most of them achieve significant power savings in comparison to conventional circuits. From the proposed glitch tolerant logic design it can observe that by performing adiabatic switching operations there is a reduction in dynamic energy dissipation. To minimize this switching power we use a factoring technique in adiabatic logic. The main drawback is that it uses junction diodes for controlling the charging and discharging of output nodal capacitance. Junction diodes are difficult to fabricate in a CMOS process. From this it can observe that the compared to existed system proposed system gives effective results.

     

     

  • References

    1. [1] C. F. Kerry, “Digital signature standard (DSS),†Nat. Inst. Standards Technol., Gaithersburg, MD, USA, FIPS PUB 186-4, 2013.

      [2] IEEE Standard Specifications for Public-Key Cryptography, IEEE Standard 1363-2000, Aug. 2000, pp. 1–228.

      [3] H. Fan and Y. Dai, “Fast bit-parallel GF(2n) multiplier for all trinomials,†IEEE Trans. Comput., vol. 54, no. 4, pp. 485–490, Apr. 2005.

      [4] A. Cilardo, “Fast parallel GF(2m) polynomial multiplication for all degrees,†IEEE Trans. Comput., vol. 62, no. 5, pp. 929–943, May 2013.

      [5] T. Beth and D. Gollman, “Algorithm engineering for public key algorithms,†IEEE J. Sel. Areas Commun., vol. 7, no. 4, pp. 458–466, May 1989.

      [6] L. Song and K. K. Parhi, “Efficient finite field serial/parallel multiplication,†in Proc. Int. Conf. Appl. Specific Syst., Archit. Processors (ASAP), Aug. 1996, pp. 72–82.

      [7] M. Nikooghadam and A. Zakerolhosseini, “Utilization of pipeline technique in AOP based multipliers with parallel inputs,†J. Signal Process.Syst., vol. 72, no. 1, pp. 57–62, Jul. 2013.

      [8] Arsalan, M.; Shams, M., "Charge-recovery power clock generators for adiabatic logic circuits," VLSI Design, 2005. 18th International Conference on , vol., no.pp. 171- 174, 3-7 Jan. 2005

      [9] Junyoung Park; Sung Je Hong; Jong Kim, "Energy-saving design technique achieved by latched pass-transistor adiabatic logic," Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on , vol., no.pp. 4693- 4696 Vol. 5, 23-26 May 2005

      [10] Willingham, D.J.; Kale, I., "Asynchronous, quasi-Adiabaticb (Asynchrobatic) logic for low-power very wide data width.applications," Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on , vol.2, no.pp. II- 257-60 Vol.2, 23-26 May 2004

      [11] Hing-mo Lam; Chi-yingTsui, "High performance and low power completion detection circuit," Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on , vol.5, no.pp. V-405- V-408 vol.5, 25-28 May 2003.

      [12] “VHDL Modeling of Booth Radix-4 Floating Point Multiplier for VLSI Designer’s Library†by Wai-Leong Pang, Kah-Yoong Chan, Sew-Kin Wong and Choon-Siang Tan in Wseas Transactions On Systems.

      [13] "VLSI design of low power digital FIR filter using PSPICE and VLSI design of high speed digital FIR filter using VERILOG HDL." (2013). Chapter 5 by Vigneswaran, T.

      [14] Efficient Implementation of 16-bit Multiplie Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog†by AddankiPurna Ramesh, Dr. A.V.N. Tilak and Dr. A.M. Prasad inInternational Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012

      [15] “Review Article: Efficient Multiplier Architecture In VLSI Design†by M. Jeevitha, R.Muthaiah and P.SwaminathanininJournal of Theoretical and Applied Information Technology 2012.Vol. 38 No.2.

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    Naga Ganesh, A., Cholines Pedapudi, M., V. Apparao, N., & ., . (2018). Design a Glitch Tolerant Adiabatic Dynamic Logic Circuits for Cryptography. International Journal of Engineering & Technology, 7(4.19), 402-406. https://doi.org/10.14419/ijet.v7i4.19.23173