A novel design of low-power reversible carry selects adder employing MPFA

  • Authors

    • R. M.Bommi Sathyabama Institute of Science and Technology
    • Dr. S.SelvakumarRaja
    2019-02-15
    https://doi.org/10.14419/ijet.v7i4.23138
  • CSLA, Fredkin Gate (FG), MPFA, Garbage Outputs, and Delay

  • In VLSI technology, power dissipation is of major concern next to speed. Due to development in technology, the necessity of fast an efficient high performance processing units has become inevitable. The circuitry of Carry Select Adder (CSLA) promises rapid dispensation in ALU and furthermore optimization can be accomplished. The proposed work encompasses the makeup of reversible design of Carry Select Adder using Modified Peres Full Adder (MPFA) and Fredkin Gate (FG). It is observed that the proposed CSLA is area efficient and attained 70% low power dissipation. The reversible CSLA is synthesized in Xilinx environment and simulated by means of ISE simulator. The reversible CSLA proposed showed multi fold advantages in terms of area- power – delay.

     

  • References

    1. [1] N. Weste and K. Eshragian, “Principle of CMOS VLSI designs: a system perspectiveâ€, 2nd ed., Addison-Wesley, 1993.

      [2] K. Rawat, T. Darwish, and M. Bayoumi, “A Low Power and Reduced Area Carry Select Adderâ€,The 45th Midwest Symposium on Circuits and Systems, Tulsa, OK, 2002, pp. I-467-I-470.https://doi.org/10.1109/MWSCAS.2002.1187259.

      [3] T. Y. Chang and M. J. Hsiao, “Carry-select adder using ripple-carry adderâ€, Electronic Letters., vol. 34, 1998, pp. 2101-2103.https://doi.org/10.1049/el:19981706.

      [4] B. Amelifard, F. Fallah and M. Pedram, “Closing the gap between carry select adder and ripple carry adder: a new class of low-power high-performance addersâ€, Sixth International Symposium on Quality of Electronic Design, San Jose, CA, USA 2005, pp. 148 - 152.https://doi.org/10.1109/ISQED.2005.131.

      [5] Y. He, C.H. Chang, and J. Gu, “An area efficient 64-bit square root carry-select adder for low power applicationsâ€, IEEE International Symposium on Circuits and Systems, Vol. 4, 2005, pp. 4082 - 4085.

      [6] Y. Chen, H. Li. Roy and K. C. Kok, “Cascaded carry-select adder: a new structure for low-power CSA designâ€, Proceedings of the 2005 International Symposium on Low Power Electronics and Design, San Diego, CA, USA, 2005 pp. 115 – 118.

      [7] A. Neve, H. Schettler, and T. Ludwig, “Power-delay product minimization in high-performance 64-bit carry-select addersâ€, IEEE Transactions on Very Large Scale Integration Systems, 2004,Vol. 12,Iss. 3, pp. 235 – 244.https://doi.org/10.1109/TVLSI.2004.824305.

      [8] T. Toffoli., “Reversible Computingâ€, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science, 1980.

      [9] E. Fredkin and T. Toffoli, “Conservative logic,†International Journal of Theoretical Physics, 1982, Vol. 21, pp.219–253.https://doi.org/10.1007/BF01857727.

      [10] H.R.Bhagyalakshmi and M.K.Venkatesha, ‘Optimized reversible BCD adder using new reversible logic gates’, Journal of Computing, 2010, Volume 2, Issue 2, ISSN 2151-9617 arXiv:1002.3994v1.

      [11] A. Tyagi, “A reduced area scheme for carry-select addersâ€,IEEE Trans. on Computer, 1993, vol. 42, pp. 1163- 1170.https://doi.org/10.1109/12.257703.

      [12] B.Ramkumar, H. M.Kittur, and P. M. Kannan,"ASIC Implementation of Modified Faster Carry Save Adder,", Eur.J.Sci.Res.,2010, vol.42,no.1,pp53-58.

      [13] T.Y.Ceiang and M.J.Hsiao,"Carry select adder using single ripple carry adder,â€,Electronic.Letters, Oct.1998. vol.34, no.22, pp.2101-2103. https://doi.org/10.1049/el:19981706.

      [14] Y.Kim and L.S.Kim,"64-bit carry select adder with reduces area," Electronics.Letters,May 2001. vol.37, no.10, pp.614-615.https://doi.org/10.1049/el:20010430.

      [15] IEEE transaction on very large scale integration system,"Low-Power and Area efficent Carry select Adder,"B.Ramkumar and Harish M.Kittur, Feb 2012, Vol.20,pp. 371-375.

      [16] R. Landauer. Irreversibility and heat generation in the computing process. IBM Journal of Research and Development, 1961, Vol5 Issue 3, pp.183-191.https://doi.org/10.1147/rd.53.0183.

      [17] C. H. Bennett. Logical reversibility of computation. IBM Journal of Re- search and Development, 1973, Vol17 Issue6, pp.525-532.https://doi.org/10.1147/rd.176.0525.

      [18] K.Prudhvi Raj and Y.Syamala, Transistor Level Implementation of Digital Reversible Circuits ,International Journal of VLSI design & Communication Systems (VLSICS) 2014,Vol.5, Issue.6, pp.43-61

      [19] R.M.Bommi and Dr.SSelvakumar Raja, 2016, Australian Journal of Basic and Applied Sciences, January 2016, Vol 10, Issue 1, Pages: 214-218.

      [20] Susan Christina, X., M. Sangeetha Justine, K. Rekha, U. Subha, R. Sumathi,Realization of BCD adder usingreversible logic-IJCTE, 2010, Vol 2, Issue 3, pp. 1793-8201.

      [21] Ming-Cui Li &Ri-Gui Zhou, A novel reversible carry-selected adder with low latency, International Journal of Electronics, , 2016, Vol 103, Issue 7, pp. 1202-1215.https://doi.org/10.1080/00207217.2015.1092595.

      [22] J. Woopyo, and R. Kaushik. “Robust High-Performance Low-Power Carry Select Adderâ€, Design Automation Conference, Jan 2003, pp. 503 - 506.

      [23] Design of Compact and Low Power Reversible Comparator, 2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT).

      [24] V. S. P. Nayak, N. Ramchander, R. S. Reddy, T. H. S. P. Redy and M. S. Reddy, "Analysis and design of low-power reversible carry select adder using D-latch," 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT),Bangalore, 2016, pp. 1917-1920."https://doi.org/10.1109/RTEICT.2016.7808169.

      [25] Bommi, R.M. & Selvakumar Raja,S. Mobile Network & Applications (2018). https://doi.org/10.1007/s11036-018-1200-2.

  • Downloads

  • How to Cite

    M.Bommi, R., & S.SelvakumarRaja, D. (2019). A novel design of low-power reversible carry selects adder employing MPFA. International Journal of Engineering & Technology, 7(4), 4780-4784. https://doi.org/10.14419/ijet.v7i4.23138