A novel design of low-power reversible carry selects adder employing MPFA
Keywords:CSLA, Fredkin Gate (FG), MPFA, Garbage Outputs, and Delay
In VLSI technology, power dissipation is of major concern next to speed. Due to development in technology, the necessity of fast an efficient high performance processing units has become inevitable. The circuitry of Carry Select Adder (CSLA) promises rapid dispensation in ALU and furthermore optimization can be accomplished. The proposed work encompasses the makeup of reversible design of Carry Select Adder using Modified Peres Full Adder (MPFA) and Fredkin Gate (FG). It is observed that the proposed CSLA is area efficient and attained 70% low power dissipation. The reversible CSLA is synthesized in Xilinx environment and simulated by means of ISE simulator. The reversible CSLA proposed showed multi fold advantages in terms of area- power â€“ delay.
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