FPGA implementation of Leading One Detector using Genetic Algorithm

  • Authors

    • Kishore Kumar ATA
    • Dr. Seshasayanan R
    • . .
  • LOD, Genetic Algorithm, FPGA, LNS.
  • Logarithmic conversion is a significant portion of numerous digital signals processing system, particularly in the fields of instruments design. Twelve bits of fractional accuracy demands lesser memory usage and minimum arithmetic components. The logarithmic transformation presented in this paper is able to support the logarithmic conversion of data with the number of bits up to sixteen. The proposed work circles around Look up Table (LUT) based approach and follow a decimal linear estimation step. The implementation results shows that the proposed architecture will operate at 43.7 MHz in FPGA fabric and at 101.9 MHz in TMSC 0.18-um technology.



  • References

    1. [1] R. E. Siferd and K. H. Abed , "CMOS VLSI implementation of a low-power logarithmic converter," in IEEE Transactions on Computers, vol. 52, no. 11, pp. 1421-1433, Nov. 2003

      [2] Dongdong Chen, Younhee Choi, Li Chen, D. Teng, Khan Wahid and Seok-Bum Ko, "A novel decimal-to-decimal logarithmic converter," 2008 IEEE International Symposium on Circuits and Systems, Seattle, WA, 2008, pp. 688-691.

      [3] M. Combet, H. L. Verbeek and Van Zonneveld, "Computation of the Base Two Logarithm of Binary Numbers," in IEEE Transactions on Electronic Computers, vol. EC-14, no. 6, pp. 863-867, Dec. 1965

      [4] M. F. Cowlishaw, "Decimal floating-point: algorism for computers," Proceedings 2003 16th IEEE Symposium on Computer Arithmetic, 2003, pp. 104-111

      [5] J.-P. Deschamps, G.J.A. Bioul, G.D. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems (Wiley, Hoboken, 2006)

      [6] M. A. Erle and M. J. Schulte, "Decimal multiplication via carry-save addition," Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003, 2003, pp. 348-358.

      [7] E. L. Hall, D. D. Lynch and S. J. Dwyer, "Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications," in IEEE Transactions on Computers, vol. C-19, no. 2, pp. 97-105, Feb. 1970.

      [8] IEEE, Inc., IEEE 754-2008 Standard for Floating-point Arithmetic (2008)

      [9] T. Lang and A. Nannarelli, "A Radix-10 Combinational Multiplier," 2006 Fortieth Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 2006, pp. 313-317.

      [10] J. N. Mitchell, "Computer Multiplication and Division Using Binary Logarithms," in IRE Transactions on Electronic Computers, vol. EC-11, no. 4, pp. 512-517, Aug. 1962.

      [11] Nagarajan, G., and R. I. Minu. "Multimodal fuzzy ontology creation and knowledge information retrieval." Proceedings of the International Conference on Soft Computing Systems. Springer, New Delhi, 2016.

      [12] J.M. Muller, Elementary Functions, Algorithms and Implementation (Birkhauser, Boston, 2005)

      [13] S. L. SanGregory, C. Brothers, D. Gallagher and R. Siferd, "A fast, low-power logarithm approximation with CMOS VLSI implementation," 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356), Las Cruces, NM, 1999, pp. 388-391 vol. 1.

      [14] T. Sasao, S. Nagayama and J. T. Butler, "Numerical Function Generators Using LUT Cascades," in IEEE Transactions on Computers, vol. 56, no. 6, pp. 826-838, June 2007.

      [15] MuhammedShafi. P,Selvakumar.S*, Mohamed Shakeel.P, “An Efficient Optimal Fuzzy C Means (OFCM) Algorithm with Particle Swarm Optimization (PSO) To Analyze and Predict Crime Dataâ€, Journal of Advanced Research in Dynamic and Control Systems, Issue: 06,2018, Pages: 699-707

      [16] Selvakumar, S & Inbarani, Hannah & Mohamed Shakeel, P. (2016). A hybrid personalized tag recommendations for social E-Learning system. 9. 1187-1199.

      [17] Nagarajan, G., et al. "Hybrid Genetic algorithm for medical image feature extraction and selection." Procedia Computer Science 85 (2016): 455-462.

      [18] Elangomenan, P., and G. Nagarajan. "Fuzzy-Based Multiloop Interleaved PFC Converter with High-Voltage Conversion System." Proceedings of the International Conference on Soft Computing Systems. Springer, New Delhi, 2016.

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    Kumar ATA, K., Seshasayanan R, D., & ., . (2018). FPGA implementation of Leading One Detector using Genetic Algorithm. International Journal of Engineering & Technology, 7(3.20), 616-619. https://doi.org/10.14419/ijet.v7i3.20.22953