FPGA implementation of Leading One Detector using Genetic Algorithm

 
 
 
  • Abstract
  • Keywords
  • References
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  • Abstract


    Logarithmic conversion is a significant portion of numerous digital signals processing system, particularly in the fields of instruments design. Twelve bits of fractional accuracy demands lesser memory usage and minimum arithmetic components. The logarithmic transformation presented in this paper is able to support the logarithmic conversion of data with the number of bits up to sixteen. The proposed work circles around Look up Table (LUT) based approach and follow a decimal linear estimation step. The implementation results shows that the proposed architecture will operate at 43.7 MHz in FPGA fabric and at 101.9 MHz in TMSC 0.18-um technology.

     

     


  • Keywords


    LOD, Genetic Algorithm, FPGA, LNS.

  • References


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Article ID: 22953
 
DOI: 10.14419/ijet.v7i3.20.22953




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