Optimize Power in Integrated Circuits by Simple Power-Critical Nets Re-routing

  • Abstract
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  • Abstract

    This work presents a new technique of the integrated circuit (IC) physical conception flow aiming to reduce the interconnexion consumption. The technique ranks nets based on their power consumption, then drive the global route prioritizing critical nets in term of power consumption. For maximum optimization, the re-routing considered only 30% of total nets that consume 88% of the total power. The technique was implemented and gave experimental results on a high-speed circuit (2GHz) realized with the 7-nm technology node. The goal was to achieve a significant power reduction with no degradation of the circuit performances and maintaining acceptable congestion overflow when routing the interconnections. The new nets re-routing power-aware performs an improvement of 12% of targeted data nets switching power and a 6% of the entire design total power.

  • References

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Article ID: 22880
DOI: 10.14419/ijet.v7i4.16.22880

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