Optimization of PFC SEPIC Converter Parameters Design for Minimization of THD and Voltage Ripple
Keywords:Optimization Parameter Design, Output Voltage Ripple, Power Factor Correction, SEPIC Converter, Total Harmonic Distortion.
This paper discusses the current total harmonic distortion (THDi) and voltage ripple minimization of SEPIC converter based on parameters design optimization. This conventional PFC SEPIC converter is designed to operate in discontinuous conduction mode in order to achieve almost unity power factor. The passive components, i.e., inductor and capacitor are designed based on switching frequency and resonant frequency. Meanwhile, the ranges of duty cycle for buck and boost operations are between 0<D<0.5 and 0.5<D<1, respectively, for the output voltage variation of the converter. The principle of the parameters design optimization is based on the balancing energy compensation between the input capacitor and output inductor. The experimental results show that, the current THD is reduced to 2.66% from 70.9% after optimization process is conducted. Furthermore, it is confirmed that the output voltage ripple frequency is always double from the input line frequency, fL = 2foutand the output voltage ripple is always lower than the maximum input voltage ripple. Therefore, the designed parameters of the experimental converter is confirmed with approximately 65 W of the converter output power.
 Ponniran A, Orikawa K & Itoh JI, â€œModular multi-stage Marx topology for high boost ratio DC/DC converter in HVDCâ€, in 2015 IEEE International Telecommunications Energy Conference (INTELEC), (2015), pp. 1â€“6.
 Ponniran A, Orikawa K & Itoh JI, â€œFundamental Operation of Marx Topology for High Boost Ratio DC-DC Converterâ€, IEEJ J. Ind. Appl., Vol. 5, No. 4, (2016), pp. 329â€“338.
 Zeljkovic S, Reiter T & Gerling D, â€œSingle-Stage Reconfigurable DC/DC Converter for Wide Input Voltage Range Operation in (H)EVsâ€, IEEJ J. Ind. Appl., Vol. 4, No. 4, (2015), pp. 424â€“433.
 Ponniran AB, Member S, Orikawa K & Itoh MJ, â€œMinimization of Passive Components in Multi-level Flying Capacitor DC-DC Converterâ€, IEEJ J. Ind. Appl., Vol. 5, No. 1, (2015), pp. 10â€“11.
 Yang HT & Chiang HW, â€œImplementation of bridgeless Cuk power factor corrector with positive output voltageâ€, in 2014 International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE ASIA), (2014), pp. 2100â€“2107.
 Kasiran AN, Ponniran A, Harimon MA & Hamzah HH, â€œA Study of 4-level DC-DC Boost Inverter with Passive Component Reduction Considerationâ€, J. Phys. Conf. Ser., Vol. 995, No. 1, (2018), pp. 12062.
 Ponniran AB & Kasiran MANB, â€œParameters design evaluation in 3-level flying capacitor boost converterâ€, in 2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE), (2017), pp. 195â€“199.
 Yatim MH et al., â€œSymmetrical and asymmetrical multilevel inverter structures with reduced number of switching devicesâ€, Indones. J. Electr. Eng. Comput. Sci., Vol. 11, No. 1, (2018), pp. 144â€“151.
 Ismail EH, â€œBridgeless SEPIC Rectifier With Unity Power Factor and Reduced Conduction Lossesâ€, IEEE Trans. Ind. Electron., Vol. 56, No. 4, (2009), pp. 1147â€“1157.
 Prudenzi A, Grasselli U & Lamedica R, â€œIEC Std. 61000-3-2 harmonic current emission limits in practical systems: need of considering loading level and attenuation effectsâ€, in 2001 Power Engineering Society Summer Meeting. Conference Proceedings (Cat. No.01CH37262), Vol. 1, (2001), pp. 277â€“282.
 Ekkaravarodome C, Buree N & Jirasereeamornkul K, â€œAn input current shaper using a Class-DE rectifier to meet IEC 61000-3-2 Class-C standard processing a small part of the total powerâ€, in 2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, (2012), pp. 1â€“4.
 Bakar AA, Utomo WM, Zulkifli SA, Sulaiman E, Ahmad MZ & Jenal M, â€œDC-DC Interleaved Boost Converter using FPGAâ€, in 2013 IEEE Conference on Clean Energy and Technology (CEAT), (2013), pp. 97â€“100.
 Afarulrazi AB, Wahyu MU, Taufik T, Aizam S & Yonis M, â€œDesign of Analog to Digital Converter for DC to DC Boost Converter with Constant Output Voltageâ€, in The 3rd International Conference on Computer Engineering and Mathematical Sciences (ICCEMS 2014) Design, (2014), pp. 800â€“804.
 Ishizuka Y, Nagata S, Takasaki M & Hirose T, â€œStatic Characteristic Analysis of Proposed Bi-Directional Dual Active Bridge DC-DC Converterâ€, IEEJ J. Ind. Appl., Vol. 4, No. 5, (2015), pp. 602â€“610.