A novel hybrid error detection and correction method using VHDL


  • Adham Hadi Saleh
  • Omar A. Imran
  • Weaam Talaat Ali
  • Adnan M. Taha
  • Wisam Najm Al-Din Abed




In this paper, we proposed a novel hybrid technique to Error Detection and Correction (EDAC) which is based on merging of two types of linear block codes: Hamming code and CRC (Cyclic Redundancy Check) at the same system. This technique is corrected all types of error by retransmitted or by Forward error correction (FEC). This technique is simply and achieves higher reliability, accuracy and security as compared with other similar methods. The system algorithms is designed and simulation using VHDL ((VHSIC (Very High Speed Inte-grated Circuit Hardware Description Language) to be implemented on FPGA kit (Field Programmable Gate Arrays) with Xilinx ISE 10.1 software program. The proposed system circuits have been designed, implemented, and corrects any types of error successfully.


[1] William Stallings"Data and Computer Communications ", 10th edition, Pearson Education. Chapter 6, p.p 187-192.

[2] G.Shanthi , Dr.L.Padmasree"CHIPSCOPE Implementation of CRC circuit architecture"IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), Volume 2, Issue 1 (Mar. – Apr. 2013), PP 07-14.

[3] Forouzan, A. B. (2011)." Data Communications & Networking". McGraw-Hill Education. Chapter 10, p.p 282-285.

[4] Qusay Al-Doori and Omar Alani"A Multi Polynomial CRC Circuit for LTE-Advanced Communication Standard", 2015 seventh Computer Science and Electronic Engineering Conference (CEEC), University of Essex, UK.

[5] Shukla S. and Bergmann N. W., “Single bit error correction implementation in CRC-16 on FPGAâ€, 1n...I EEE International Conference on Field- Programmable Technology. Brisbane, Australia, 2004.

[6] Wael M El-Medany,"FPGA Implementation of CRC with Error Correction", the Eighth International Conference on Wireless and Mobile Communications, 2012.

[7] M. Sprachmann, “Automatic generation of parallel CRC circuitsâ€, IEEE Des. Test Comput. vol. 18, no. 3, pp. 108–114, May/Jun. 2001. https://doi.org/10.1109/54.922807.

[8] Adham Hadi Saleh, Kamal Mohammed Saleh and Saad Al-Azawi "Design and Simulation of CRC Encoder and Decoder Using VHDL" first International Scientific Conference of Engineering, Sciences - 3rd Scientific Conference of Engineering Science (ISCES), IEEE, 2018.

[9] Rajesh Nair, Gerry Ryan and Farivar Farzaneh" A Symbol Based Algorithm for Hardware Implementation of Cyclic Redundancy Check (CRC)" Proceedings VHDL International Users' Forum. Fall Conference, IEEE, 1997.

[10] Tongsheng Zhang, Qun Ding" Design of (15, 11) Hamming Code Encoding and Decoding System Based on FPGA" International Conference on Instrumentation, Measurement, Computer, Communication and Control,IEEE, 2011 https://doi.org/10.1109/IMCCC.2011.179.

[11] Wirda Fitriani, Andysah Putera and Utama Siahaan " Single-Bit Parity Detection and Correction using Hamming Code 7-Bit Model",International Journal of Computer Applications, Volume 154 – No.2, November 2016.

[12] N. Shep and P. Bhagat, "Implementation of Hamming code using VLSI," International Journal of Engineering Trends and Technology, vol. 4, No. 2, pp. 186-190, 2013.

[13] Adham Hadi Saleh,"Design of Hamming code for 64 bit single error detection and correction using VHDL",Diyala Journal of Engineering Sciences, Vol. 08, No. 03, pp. 22-37, September 2015.

[14] Adham Hadi Saleh "Design of Hamming Encoder and Decoder Circuits For (64, 7) Code and (128, 8) Code Using VHDL" Journal of Scientific and Engineering Research,Vol(2),No(1), , pp. 1-15, 2015.

[15] Raymond Irudayaraj I., Abdul Lateef Haroon P.S, Ulaganathan J., Shridhar S. Bilagi "Design And Verification Of Improved Hamming Code (Ecc) Using Verilog",International Journal Of Electrical, Electronics And Data Communication, Volume-5, Issue-4, Aprl.-2017.

[16] Ravi Hosamani, Ashwini S. Karne"Design and Implementation of Hamming Code on FPGA using Verilog ", International Journal of Engineering and Advanced Technology (IJEAT), Volume-4 Issue-2, December 2014.

[17] M.Y. Rhee - “Error Correcting Coding Theoryâ€, McGraw-Hill, Singapore, 1989.

[18] Goresky, M. and Klapper, A.M. Fibonacci and Galois representations of feedback-with-carry shift registers, IEEE Transactions on Information Theory, Nov 2002, Volume: 48, On page(s): 2826 –2836.

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