Low Power and Low Area Junction-less Tunnel FET Design


  • U Ragavendran
  • M Ramachandran
  • . .






TFET, Flip-flop, Low power design, low-power integrated circuits, Junctionless FET


We present Junction less Tunnel FET with Si:SiGe, Si:AlGaAs and Si:InGaAsP and investigate their DC characteristics. The proposed structures present tremendous performance at a very low supply voltage. The key idea is to study device performance, which can be exploited as a digital switching device for 22 nm technology. Comparison of different heterostructures numerical simulations indicates that ION increases from 0.0024345 to 0.006532 A/μm, when Si:SiGe is replaced with Si:InGaAsP for 22nm channel with supply voltage of 0.5V at a temperature of 300K.



[1]. P. K. Asthana, Y.Goswami, S. Basak, S. B. Rahi and B. Ghosh, “Improved Performance of Junctionless Tunnel Field Effect Transistor with Si and SiGe Hetero-Structure for Ultra Low Power Applicationsâ€, RSC Adv.,2015.

[2]. M. Jagadesh Kumar and KanikaNadda, “Bipolar Charge- Plasma Transistor:A Novel Three Terminal Device†, IEEE Transactions On Electron Devices, VOL. 59, NO. 4, April 2012.

[3]. ShiromaniBalmukundRahi, Pranav Asthana and Shoubhik Gupta, "Heterogatejunctionless tunnel field-effect transistor: future of low-power devices", Springer Science, Business Media New York 2016, November, 2016.

[4]. Satish M. Turkane, A.K. Khureshi, "Review of Tunnel Field Effect Transistor (TFET)", International Journal of Applied Engineering Research, 2016, Vol. 11.7.

[5]. Michael Riordan, Lillian Hoddeson, Conyers Herring, "TheInvention of the transistor", The American Physical Society, 1999, Reviews of Mordern Physic, Vol. 71, No. 2, published by The American Physical Society, pp.S336-S345.

[6]. Ragavendran, U., Viral Mehta, Vishal Fegade, and M. Ramachandran. "Dynamic Analysis of Single Fold Symmetric Composite Laminates." International Journal of Civil Engineering and Technology 8, no. 11 (2017): 536-545.

[7]. Merzbacher, Eugen, "The Early History of Quantum Tunneling", Physics Today, American Institute of Physics, August, 2002.

[8]. Jakubowski, Lidia Åukasiak and Andrzej, "History of Semiconductors", January, 2010, Journal of Telecommunications and InformationTechnology.

[9]. J.J. Liou, A. Ortiz-Condez and F.G. Sanchez, "Extraction of the threshold voltage of MOSFETs: an overview",HongKong : Electron Devices Meeting, Proceedings, IEEE, August,1997.

[10]. Ragavendran, U., M. Ramkumarraja, and M. Ramachandran. "Low power VLSI architecture for LTEx binary to gray converters." In 2017 3rd International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT), pp. 107-109. IEEE, 2017.

[11]. Ghosh, M. W. Akram and Bahniman, "Analog performance of double gate junctionless tunnel field effect transistor", Journal of Semiconductors, July, 2014, Vol. 35.7.

[12]. Duraisamy, K, Ragavendran, U ‘Low Power Analog Multiplier Using MIFGMOS’, Journal of Computer Science (JCS), vol. 9, no. 4, pp. 514-520, 2013.

[13]. Flynn, Grant McFarland and Michael "Limits of Scaling MOSFETs", Departments of Electrical Engineering and Computer Science, Stanford University, January,1995.

[14]. Esfandyarpour, Rahim, "Tunnel Field EffectTransistor" Standford University, June, 2012.

[15]. U. Ragavendran, M. Ramachandran, Low Power Spike Analysis of Neuron Circuit with Floating Gate Transistors (FGMOS), International Journal of Pure and Applied Mathematics 119(12), 2018

[16]. Synopsys, Sentaurus TCAD, Industry-Standard Process and Device Simulators; Datasheet.2012.

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How to Cite

Ragavendran, U., Ramachandran, M., & ., . (2018). Low Power and Low Area Junction-less Tunnel FET Design. International Journal of Engineering & Technology, 7(3.1), 155–157. https://doi.org/10.14419/ijet.v7i3.1.17076
Received 2018-08-08
Accepted 2018-08-08
Published 2018-08-04