Low Power and Low Area Junction-less Tunnel FET Design

  • Abstract
  • Keywords
  • References
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  • Abstract

    We present Junction less Tunnel FET with Si:SiGe, Si:AlGaAs and Si:InGaAsP and investigate their DC characteristics. The proposed structures present tremendous performance at a very low supply voltage. The key idea is to study device performance, which can be exploited as a digital switching device for 22 nm technology. Comparison of different heterostructures numerical simulations indicates that ION increases from 0.0024345 to 0.006532 A/μm, when Si:SiGe is replaced with Si:InGaAsP for 22nm channel with supply voltage of 0.5V at a temperature of 300K.


  • Keywords

    TFET, Flip-flop, Low power design, low-power integrated circuits; Junctionless FET

  • References

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Article ID: 17076
DOI: 10.14419/ijet.v7i3.1.17076

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