Design, Implementation and Analysis of 8T SRAM Cell in Memory Array

 
 
 
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  • Abstract


    In modern VLSI designs, static random access memory plays a vital role because of its high performance and low power consumption qualities. As technology is scale down, the importance of the power analysis and leakage current of memory design is increasing. This paper describes about the 1 KB size memory design using SRAM. The proposed design of 8T SRAM single cell in implemented in array structure of size 32x32.The design structure reduces the power by 75% by reducing the leakage current. The proposed 8T SRAM cell is implemented and analyzed in 90nm technology using Digital schematic and Micro wind software.

     


  • Keywords


    WL, BL, BLB and SRAM

  • References


      [1] Tae Woo Oh, Han wool Jeong, Kyoman Kang, Juhyun Park, Younghwi Yang, and Seong-Ook Jung, Power-Gated 9T SRAM Cell for Low-Energy Operation” IEEE Transactions On Very Large Scale Integration Systems (2016).

      [2] Zhou Keji, Wang Pengjun “Design of power balance SRAM for DPA-resistance” Journal of Semiconductors, Vol.37, No.4, April 2016.

      [3] B. Kaleeswari, Dr. S. KajaMohideen ,”Analysis of Leakage current in 8T SRAM for low power application “Journal of social, technological and environmental sciences, Sep 2017,Vol No 6 pp-601-610.

      [4] Jaspreet Kaur, Candy Goyal,” Comparative Analysis of Low Leakage SRAM Cell at 32nm Technology” International Journal of Computer Applications, Volume 133 – No.12, January 2016.

      [5] Shalini Singh, Vishwas Mishra, Low Power Consuming 1KB (32x32) Memory Array Using Compact 7T SRAM Cell , International Journal of Advanced Engineering and Global Technology Vol-04, Issue-01, January 2016.

      [6] G. Apostolidis, D. Balobas and N. Konofaos, “Design and Simulation of 6T SRAM Cell Architectures in 32nm Technology” Journal of Engineering Science and Technology Review Jan 2016, pp-145 – 149.

      [7] AbhishekMathur, ArunJayachandran, RamyaVenumbaka “Low Leakage SRAM design using sleep transistor stack”, (2013).

      [8] P.S.G. SRIDEVI, P.V.K. CHAITANYA,” New Leakage Reduction Techniques”, International Journal of Advances in Science Engineering and Technology, Volume- 1, Issue- 1, July-2013.

      [9] Saurabh Khandelwal, Balwinder Raj Leakage Current and Dynamic Power Analysis Of Finfet Based 7T SRAM At 45nm Technology, The International Arab Conference on Information Technology (ACIT’2013).

      [10] Atluri .Jhansi rani, K .Harikishore, Fazal Noor Basha,,V.G. SanthiSwaroop, L. VeeraRaju , ” Designing and Analysis of 8 Bit SRAM Cell with Low Subthreshold Leakage Power “ in International Journal of Modern Engineering Research, Vol.2, Issue.3 (2012).

      [11] Eitan N. Shauly,“ CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations in Journal of low power Electronics(2012).

      [12] T. H. Kim, J. Liu, J. Keane, and C. H. Kim, “A 0.2 V, 480 kb sub threshold SRAM with 1 k cells per bit line for ultra-low-voltage computing ,” IEEE J. Solid-State Circuits, vol. 43, no. 2, (2008) pp. 518–529.

      [13] G. Ramprabu, S. Nagarajan, “Design and Analysis of Novel Modified Cross Layer Controller for WMSN”, Indian Journal of Science and Technology, Vol 8(5), March 2015, pp.438-444.


 

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Article ID: 16808
 
DOI: 10.14419/ijet.v7i3.1.16808




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