High Speed RADIX-2 Butterfly Structure Using Novel Wallace Multiplier

  • Authors

    • Garima Thakur
    • Harsh Sohal
    • Shruti Jain
    2018-06-25
    https://doi.org/10.14419/ijet.v7i3.4.16777
  • Fast Fourier Transform, FPGA, Kogge Stone Adder, Wallace multiplier, Xilinx ISE 14.1.

  • In Signal Processing applications the arithmetic units mainly consists of adders and multipliers. These arithmetic units are used in to enhance the performance of Fast Fourier Transform (FFT) Butterfly structure implementation. This paper discusses the addition and multiplication algorithms for parameters like speed, area and power. The best suited among all adders are Kogge Stone Adder (KSA) while among multipliers are Wallace multiplier(WM) which is used for the implementation of the FFT structure. Verilog coding is used for implementation of circuit and the tool used is Xilinx ISE 14.1 Design suite.

     

  • References

    1. [1] Bais K. & Ali Z., “Comparison of various adder designs in terms of delay and areaâ€, International journal of science and research (IJSR), Volume 5, Issue 5, May 2016.

      [2] Anjana.R, Abishna.B, Harshitha.M.S., Abhishek.E, Ravichandra V., Suma M. S., “Implementation of Vedic Multiplier using Kogge-Stone Adderâ€, International Conference on Embedded Systems - (ICES ), 2014.

      [3] S. Rajaram, K. Vanithamani, “Improvement of Wallace multipliers using Parallel prefix addersâ€, International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), 2011.

      [4] S.Murugeswari, S.Kaja Mohideen, “Design of Area Efficient and Low Power Multipliers using Multiplexer based Full Adderâ€, 2nd International Conference on Current Trends in Engineering and Technology, ICCTET, 2014.

      [5] A. K. Singh & A. Nandi, “Design of Radix 2 Butterfly Structure using Vedic multiplier and CLA on Xilinxâ€, Proc. IEEE Conference on Emerging Devices and Smart Systems, 3-4 March 2017.

      [6] A. Thomas, A. Jacob, S. Shibu & S. Sudhakaran, “ Comparison of Vedic Multiplier with Conventional Array and Wallace Tree Multiplierâ€, International Journal of VLSI System Design and Communication Systems, Vol. 04, Issue. 04, April 2016.

      [7] A. Maiti , K. Chakraborty, R. Sultana & S. Maity, “Design and implementation of 4-bit Vedic Multiplierâ€, International Journal of Emerging Trends in Science and Technology, Vol. 03, Issue 05, Pages 3865-3868, May 2016.

      [8] A. Mankar, FPGA Implementation of Fast Fourier Transform Core using NEDA, Mtech Thesis , National Institute of Technology, Rourkela, 2011-2013.

      [9] M. Patrikar & V. Tehre, “Design and Power Measurement of 2 and 8 Point FFT using Radix-2 Algorithm for FPGA Implementationâ€, IOSR Journal of VLSI and Signal Processing, Vol. 7, Issue 1, Jan-Feb 2017, PP 44-48.

      [10] J. G. Proakis & D. G. Manolakis, â€Digital Signal Processing Principle, Algorithms, and Applicationsâ€, 4th Edition, 2007, Prentice Hall India Publications.

      [11] M. J. Rashmi, G. S. Biradar & M. Patil, “Efficient VLSI Architecture using DIT-FFT Radix-2 and Split Radix FFT Algorithmâ€, International Journal for Technological Research in Engineering, Vol. 1, Issue 10,June 2014.

  • Downloads

  • How to Cite

    Thakur, G., Sohal, H., & Jain, S. (2018). High Speed RADIX-2 Butterfly Structure Using Novel Wallace Multiplier. International Journal of Engineering & Technology, 7(3.4), 213-217. https://doi.org/10.14419/ijet.v7i3.4.16777