Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop

Authors

  • Thejusraj. H
  • Prithivi Raj
  • J Selvakumar
  • S Praveen Kumar

DOI:

https://doi.org/10.14419/ijet.v7i3.12.16553

Published:

2018-07-20

Keywords:

Current Starved VCO, PLL, Ring VCO.

Abstract

This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.

References

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How to Cite

H, T., Raj, P., Selvakumar, J., & Praveen Kumar, S. (2018). Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop. International Journal of Engineering & Technology, 7(3.12), 871–875. https://doi.org/10.14419/ijet.v7i3.12.16553

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Received 2018-07-30
Accepted 2018-07-30
Published 2018-07-20