Design of All Digital Phase Locked Loop for Wireless Applications


  • Swetha R
  • J Manjula
  • A Ruhan bevi





All Digital Phase Locked Loop(ADPLL), Dig-ital Loop Filter, Ring Oscillator, Delay Cells, Programmable divider, Cadence


This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.



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How to Cite

R, S., Manjula, J., & Ruhan bevi, A. (2018). Design of All Digital Phase Locked Loop for Wireless Applications. International Journal of Engineering & Technology, 7(3.12), 836–840.
Received 2018-07-29
Accepted 2018-07-29
Published 2018-07-20