Design of All Digital Phase Locked Loop for Wireless Applications

  • Abstract
  • Keywords
  • References
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  • Abstract

    This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.


  • Keywords

    All Digital Phase Locked Loop(ADPLL), Dig-ital Loop Filter, Ring Oscillator, Delay Cells, Programmable divider,Cadence

  • References

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      [3] A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6 (14.5) System Efciency at 6-dBm (0-dBm) Pout, IEEE 2017.

      [4] Zhiqiang Huang and Howard C. Luong, Fellow, Design and Analysis of Millimeter-Wave Digitally Controlled Oscillators With C-2C Exponen-tially Scaling Switched-Capacitor Ladder , IEEE 2017.

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Article ID: 16513
DOI: 10.14419/ijet.v7i3.12.16513

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