Design of Reconfigurable Block FIR Filter Architecture and Implementation on Hardware

Authors

  • Suji S
  • Radhika P

DOI:

https://doi.org/10.14419/ijet.v7i3.12.16511

Published:

2018-07-20

Keywords:

Reconfigurable block FIR filter, Register unit, Inner product unit(IPU), Pipelined adder, xilinx vivado 2015.4, Zynq xc7020, Cadence.

Abstract

In this paper, a reconfigurable block FIR filter which supports variable filter length is proposed. This recon-figurable block FIR filter uses block based design. Hence, this is an algorithm free architecture. This proposed filter can be used for 5G air interface.The proposed filter produces more efficient power reduction than that of the other filter.The number of LUTs and registers are also reduced in the reconfigurable block FIR filter. The designed filter has been implemented in the ZYNQ xc7020 hardware device using the vivado 2015.4.The technique used for hardware implementation is the IP creation and debug-ging.The debugging helps in the monitoring and triggering the hardware device.

 

 

References

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How to Cite

S, S., & P, R. (2018). Design of Reconfigurable Block FIR Filter Architecture and Implementation on Hardware. International Journal of Engineering & Technology, 7(3.12), 826–830. https://doi.org/10.14419/ijet.v7i3.12.16511

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Received 2018-07-29
Accepted 2018-07-29
Published 2018-07-20