Designing and Implementation of Efficient (2i x j) Reversible RAM-Array Module

  • Authors

    • Srija Alla
    • Bharathi S H
    2018-07-20
    https://doi.org/10.14419/ijet.v7i3.12.16506
  • Quantum – Cost, Reversible Logic-Gates, Reversible D- Flip Flops, Reversible Random Acces Memory (RRAM) .

  • In the modern digital-world, power dissipation in microprocessors is becoming a significant challenge for the researchers to design an efficient reversible logic circuit. Thus, study on reversible logic design has been rapidly increased in present days for its application in Nano technology as well as in low energized VLSI design etc. In this current study, have realized a QC (i.e. quantum-cost) efficient (2i x j) reversible RAM array module with (3 x 3) New Modified Fredkin (NMF) reversible gate. Additionally, have introduced a Reversible D-Flip-Flop (RDFF) with less QC, and Reversible (i x 2i) decoder which produces the effective results in terms of QC and garbage-outputs. Finally, the study analyzed the designed architecture in terms of worst case delay.

     

     

  • References

    1. [1] Nowrin, Sadia, Papiya Nazneen, and Lafifa Jamal. "Design of a Compact Reversible Read-Only-Memory with MOS Transistors." arXiv preprint arXiv:1610.06088 (2015).

      [2] D. Michael Miller , Dmitri Maslov , GerhardW. Dueck, “A transformation based algorithm for reversible logic synthesisâ€, Annual ACM IEEE Design Automation Conference,Proceedings of the 40th annual Design Automation Conference, Anaheim, CA, USA Pages: 318 – 323.

      [3] Sharmin, Farah, et al. "Design of a compact reversible random access memory." 4th IEEE International Conference on Computer Science and Information Technology. Vol. 10. 2011.

      [4] Mamun, Md, Selim Al, and Syed Monowar Hossain. "Design of reversible random access memory." arXiv preprint arXiv:1312.7354 (2013).

      [5] Hamsa, S., H. Basavaraj, and A. G. Ananth. "Design of SRAM Array using Reversible Logic for Low Power Non-volatile applications." (2017).

      [6] M.Sharma, M.Kakkar,M.Sharma, â€Memory Design Using Logical Gatesâ€, International Journal For Research In Applied Science And Engineering Technology(Ijraset), Vol.2Issue IX, September2014, ISSN: 2321-9653.

      [7] M.HaghParasat and K.Navi, “ A Novel reversible Full Adder circuit for Nanotechnology based systemsâ€, Journal of applied sciences,2007 Asian Network for Scientific Information

      [8] Mamun, Md, Selim Al, and Syed Monowar Hossain. "Design of reversible random access memory." arXiv preprint arXiv:1312.7354 (2013).

      [9] Ali, Md Belayet, Md Mosharof Hossin, and Md Eneyat Ullah. "Design of reversible sequential circuit using reversible logic synthesis." International Journal of VLSI Design & Communication Systems 2.4 (2011): 37.

      [10] Naguboina, Gopi Chand, and K. Anusudha. "Design and implementation of programmable read only memory using reversible decoder on FPGA." Signal Processing, Communication and Networking (ICSCN), 2017 Fourth International Conference on. IEEE, 2017.

      [11] Majumdar, Ritajit, and Sandeep Saini. "A novel design of reversible 2: 4 decoder." Signal Processing and Communication (ICSC), 2015 International Conference on. IEEE, 2015.

      [12] Chandana, S., et al. "Design of register file using reversible logic." Circuit, Power and Computing Technologies (ICCPCT), 2016 International Conference on. IEEE, 2016.

      [13] Bruce, J. W., et al. "Efficient adder circuits based on a conservative reversible logic gate." VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on. IEEE, 2002.

      [14] Bhandari, Jugal. "A novel design approach of low power consuming Decoder using Reversible Logic gates." International Journal 4.1 (2016): 210-214.

      Yelekar, Prashant R., and Sujata S. Chiwande. "Introduction to reversible logic gates & its application." 2nd National Conference on Information and Communication Technology. 2011.

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  • How to Cite

    Alla, S., & S H, B. (2018). Designing and Implementation of Efficient (2i x j) Reversible RAM-Array Module. International Journal of Engineering & Technology, 7(3.12), 808-812. https://doi.org/10.14419/ijet.v7i3.12.16506