Design and Analysis of 8-bit Vedic Multiplier in 90nm Technology using GDI Technique
DOI:
https://doi.org/10.14419/ijet.v7i3.12.16496Published:
2018-07-20Keywords:
Vedic Multiplier, Urdhva-Tiryakbyham, Gate Diffusion Input, 90 nm technology.Abstract
Vedic mathematics is an old mathematics which is more effective than other mathematic procedures. Vedic maths is utilized as a part of numerous applications, for example, hypothesis of numbers, compound duplications, squaring, cubing, square root and solid shape root and so on. Absolutely there are 16 sutras and 14 sub-sutras in Vedic maths. Among those sutras, just 3 sutras and 2 sub-sutras are utilized for augmentation. Multiplier is a very important part of a microprocessor as multiplication is performed continuously in all calculative procedures. This paper is in importance of a 8-bit multiplier designed in 90 nm technology. Urdhva-Tiryakbyham is the sutra that is used for multiplication in Vedic mathematics. Actualizing the different scientific operations utilizing Vedic Mathematics causes us accomplish better speed, bring down unpredictability and higher execution.[2] The technique used is Gate Diffusion Input (GDI) which is a more refined way to design a circuit which less complex than circuits designed by other techniques.
References
[1] C.Selvakumari, M.Jeyaprakash, A.Kavitha,“Transistor Level Implementation of a 8-bit Multiplier using Vedic mathematics in 180nm technology.†International Conference on Computing for sustainable Global Development, 2016.
[2] Yogendri, Anil kumar Gupta, “Design of High performance 8-bit Vedic Multiplier.†978-1-5090-0673-1/16/$31.00,2016 IEEE.
[3] Anannya Maiti,Koustuv Chakraborty, Razia Sultana, Santanu Maity, “ Design and implementation of 4 bit vedic multiplier.†International Journal of Emerging Trends in Science and Technology,2016.
[4] Rajesh Mehra , Ranbirjeet Kaur, “Power and Area Efficient CMOS Half Adder using GDI Techique.â€International Journal of Engineering Trends and Technology(IJETT),June 2016.
[5] Suryasnata Tripathy, LB Omprakash, Sushanta K.Mandal,B S Patro, “Low Power Multiplier Architectures using Vedic Mathematics in 45nm Technology for High Speed Computing.†2015 International Conference on Communication , Information &Computing Technology(ICCICT).
[6] Arkadiy Mogenshtein, Alexander Fishand Israel A.Wagner, “Gate-Diffusion Input(GDI): A Power-Efficient Method for digital Combinatorial Circuits.†IEEE Transactionson Very large scale integration systems,Vol. 10,No.5,October 2002.
[7] Padmanabhan Balasubramanian and Johince John, “ Low Power Digital design using modified GDI method.â€0-7803-9727-4/06/@20.00 2006 IEEE.
[8] R.Anitha and Sarat Kumar Sahoo , “VLSI Implementation of Discrete Linear Convulation using Vedic Mathematics(Real and Complex Numbers).†International Journal ofApplied Engineering Research.
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Accepted 2018-07-29
Published 2018-07-20