Performance Evaluation of Ring Counter using Gated Clock


  • Pushpa Mala S
  • Bharath S P
  • Anjum .
  • Aniket Kumar
  • Debolina Kundu





Gated clock, Johnson Counter, Ring counter.


Minimizing Power dissipation is one of the major concerns in the VLSI industry.Due the rapid growth in technology, there is a tremendous reduction in the chip size. Minimum power consumption has become a priority.In this paper, we propose a low power design techniquefor Ring counter using gated clock.In this paper, we demonstrate the working of ring counter using gated clock.The results are illustrated in Xilinx. The simulation results and the synthesis outputis shown.




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How to Cite

Mala S, P., S P, B., ., A., Kumar, A., & Kundu, D. (2018). Performance Evaluation of Ring Counter using Gated Clock. International Journal of Engineering & Technology, 7(3.12), 701–702.
Received 2018-07-28
Accepted 2018-07-28
Published 2018-07-20