Reduction of Power Consumption using Joint Low Power Code with Crosstalk Avoidance Code in Case of Crosstalk and Random Burst Errors

  • Authors

    • Ashok Kumar.K
    • Dananjayan. P
    2018-07-20
    https://doi.org/10.14419/ijet.v7i3.12.15864
  • Network on Chip, Crosstalk Errors, CAC, LPC, Reliability.

  • When technology is scaling down, reliability and power issues are arise in the intercommunication of System on Chip (SoC). The intercommunication links are suffers with various noise sources like crosstalk, temperature variation and voltage deflection which lead to communication link failure. To get reliable system, the strong error detection and correction codes are required. In this proposed work, Crosstalk avoidance code detects and corrects of one bit error, two bit error and some of three bit errors. The Hybrid Automatic Re-transmission Request is also used when the CAC detects the burst error of three. Apart from this, the Low Power Codes are used to get low power consumption using Bus Invert (BI) technique in proposed work. The LPC code reduces the power consumption of interconnection wires using reducing switching activity. The performance of proposed work evaluated in Xilinx 14.7 in Vertex-6 Field Programmable Gated Array (FPGA) device. The proposed work is calculated of power consumption of codec module and interconnection wire, delay of CAC and LPC code and link swing voltage. This work provides 11.7% improvement in power consumption and presents high reliability than JTEC. The energy dissipation of wires in the proposed work is decreased 23.5% than un-coded schemes.

     

     

  • References

    1. [1] L. Benini, G. De Micheli, “Networks on chips: a new SoC paradigm,†IEEE Computer, pp. 70–78, 2002.

      [2] International Technology Roadmap for Semiconductors. Semiconductor Industry Assoc. [Online]. Available: http://public.itrs.net

      [3] Fu, B., Ampadu, P, “Error control for network-on-chip links,†New York: Springer, 2012.

      [4] Murali, S., Theocharides, T., Vijayakrishnan, N., Irwin, M.J., Benini, L., Micheli, G. De., “Analysis of error recovery schemes for networks-on-chipsâ€, IEEE design and Test of computer, vol. 22, pp. 434–442, 2005.

      [5] Bertozzi D, Benini L, Micheli GD, “Error correction schemes for on-chip communication links: The energy- reliability tradeoff,†IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, vol. 24, no. 6, pp. 818–831, 2005.

      [6] Duan, C., Tirumala, A., Khatri, S. P., “Analysis and avoidance of crosstalk in on-chip buses,†IEEE International 9th Conference Hot Interconnects, pp. 133-138, August 2001. Stanford, CA

      [7] Ganguly, A., Pande, P. P., Belzer, B., Grecu, C., “Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding,†IEEE Computer Society Annual Symposium on VLSI, March 2007, Porto Alegre.

      [8] Ganguly, A., Pande, P.P., Belzer, B., Grecu, C., “Design of low power & Reliable Networks on chips through joint crosstalk avoidance and multiple error correcting codingâ€, Journal of Electronic Testing: Theory and Appl. (JETTA), vol.24, no.1-3, pp. 67–81, 2008.

      [9] S. R. Sridhara, and N. R. Shanbhag, “Coding for System on chip Networks: A Unified Framework,†IEEE Transactions on VLSI Systems, vol. 13, no. 6, pp. 655-667, June 2005.

      [10] Rossi D, Metra C, Nieuwland AK, Katoch A, “Exploiting ECC redundancy to minimize crosstalk impact,†IEEE Design and Test of Computers, vol. 22,no. 1, pp.59–70, 2005.

      [11] Rossi D, Metra C, Nieuwland AK, Katoch A, “ New ECC for crosstalk effect minimization,†IEEE Design and Test of Computers, vol.22, no. 4, pp.340–348, 2005.

      [12] Patel KN, Markov IL, “Error correction and crosstalk avoidance in DSM buses,†IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 10, pp.1076–1080, 2004.

      [13] B. Fu, P. Ampadu, “Burst error detection hybrid ARQ with crosstalk delay reduction for reliable on chip Interconnects,†24th IEEE International Symposicium on Detect Fault Tolerance in VLSI Systems, pp.440–448, 2009, USA.

      [14] Ganguly, A., Pande, P., B Belzer., “Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnectsâ€, IEEE Transactions on very Large Scale Integration Systems, vol. 17, no.11, pp. 1626–1639, 2009.

      [15] Po Tsang Huang, Wei Hwang, “Self-Calibrated Energy-Efficient and Reliable Channels for on chip Interconnection Networksâ€, Journal of Electrical and Computer Engineering, vol. 2012, pp.1-19, 2012.

      [16] Maheswari M, Seetharaman G, “Design of a novel error correction coding with cross talk avoidance for reliable on chip interconnection networks,†International Journal of Computer Applications in Technology, vol. 49, no. 1, pp.80–88, 2014.

      [17] Yu, Q., Bo Zhang, Yan Li, Paul Ampadu., “Error Correction Integration scheme for reliable NOCâ€, Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp.3893-3896, August 2010, France.

      [18] Pande, P.P., Ganguly, A., Brett Feero, Belzer, B., “Design of low power & Reliable Networks on chip through joint crosstalk avoidance and forward error correction codingâ€, Proceedings of 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.466-476, 2006.

      [19] Ashok Kumar K, P.Dananjayan, “A Survey for Silicon on Chip Communicationâ€, Indian Journal of Science and Technology, vol. 10, no.1, pp.1-10, 2017.

      [20] Maheswari M, Seetharaman G, “Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection linksâ€, Microprocessors and Microsystems, vol. 37, no.4–5, pp.420–429, 2013.

      [21] M.R. Stan and W.P. Burleson, “Bus-invert coding for low power I/Oâ€, IEEE Transactions on VLSI Systems, vol.3, no.1, pp.49-58, 1995.

  • Downloads

  • How to Cite

    Kumar.K, A., & P, D. (2018). Reduction of Power Consumption using Joint Low Power Code with Crosstalk Avoidance Code in Case of Crosstalk and Random Burst Errors. International Journal of Engineering & Technology, 7(3.12), 62-68. https://doi.org/10.14419/ijet.v7i3.12.15864