Reduction of Power Consumption using Joint Low Power Code with Crosstalk Avoidance Code in Case of Crosstalk and Random Burst Errors
Keywords:Network on Chip, Crosstalk Errors, CAC, LPC, Reliability.
When technology is scaling down, reliability and power issues are arise in the intercommunication of System on Chip (SoC). The intercommunication links are suffers with various noise sources like crosstalk, temperature variation and voltage deflection which lead to communication link failure. To get reliable system, the strong error detection and correction codes are required. In this proposed work, Crosstalk avoidance code detects and corrects of one bit error, two bit error and some of three bit errors. The Hybrid Automatic Re-transmission Request is also used when the CAC detects the burst error of three. Apart from this, the Low Power Codes are used to get low power consumption using Bus Invert (BI) technique in proposed work. The LPC code reduces the power consumption of interconnection wires using reducing switching activity. The performance of proposed work evaluated in Xilinx 14.7 in Vertex-6 Field Programmable Gated Array (FPGA) device. The proposed work is calculated of power consumption of codec module and interconnection wire, delay of CAC and LPC code and link swing voltage. This work provides 11.7% improvement in power consumption and presents high reliability than JTEC. The energy dissipation of wires in the proposed work is decreased 23.5% than un-coded schemes.
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