Technique to Improve SNR for Sigma Delta Adcs for Audio Signals
DOI:
https://doi.org/10.14419/ijet.v7i3.6.14946Keywords:
Sigma-Delta ADC, SNR, RISR architecture, OSR, NTF, STF, noise shaping.Abstract
A RISR architecture for Sigma-delta analog to digital converters with modified noise transfer function to obtain a better performance in terms of SNR is proposed. Cascading of two modified second order modulators are done to achieve 4th order modulator. Behavioral simulations are done to study the performance of feed-forward and the modified cascaded architecture. They are designed to operate at 1.28MHz clock frequency for audio applications (OSR of 32). It is noted that SNR of 115dB is achieved by cascading of two Modified second order RISR architectures which is 8dB more than the normal RISR architecture.
Â
Â
References
[1] Schrier R & Temes GC, Understanding Delta-Sigma Data Converters. John Wiley and Sons Inc., (2005).
[2] Johns DA & Martin K, Analog Integrated Circuit Design, John Wiley and Sons Inc., (1997).
[3] Pervez M, Aziz HVS & Jan VD S, “An overview of sigma-delta convertersâ€, IEEE Signal processing magazine, Vol.13, No.1, (1996).
[4] Ki YN, Sang ML, David KS & Bruce AW, “A Low-Voltage Low-Power Sigma-Delta Modulator for Broad band analog-to-digital conversionâ€, IEEE journal of solid-state circuits, Vol.40, No.9, (2006).
[5] Ahmed G & Johans DA, “On the implementation of input- feed forward Delta-sigma modulatorsâ€, IEEE Transactions on circuits and systems, Vol.53, No.6, (2006).
[6] Baker RJ, Harry WL & David EB, CMOS Circuit Design, Layout, and Simulation, IEEE Press., (1998).
[7] Baker RJ, Harry WL & David EB, CMOS Mixed-signal Circuit Design, John Wiley and Sons Inc., (2003).
Downloads
How to Cite
Received date: July 2, 2018
Accepted date: July 2, 2018
Published date: July 4, 2018