Design and Synthesis of Restoring Technique Based Dual Mode Floating Point Divider for Fast Computing Applications

 
 
 
  • Abstract
  • Keywords
  • References
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  • Abstract


    Floating point division plays a vital role in quick processing applications. A division is one amongst the complicated modules needed in processors. Area, delay and power consumption are the main factors that play a significant role once planning a floating point dual-precision divider. Compared to different floating-point arithmetic, the design of division is way a lot of sophisticated and needs longer time. Floating point division is that the main arithmetic unit that is employed within the design of the many processors in the field of DSP, math processors and plenty of different applications. This paper relies on the dual-mode practicality of floating point division. The proposed designed architecture supports the single precision (32-bit) as well as double precision (64-bit) IEEE 754 floating point format. It uses restoring division technique for the fraction part division. This design consists of varied sub-modules like shifters, exceptional handlers, Normalizers and many more.

     

     


  • Keywords


    Floating point division, shifter, exceptional Handler, normalizer, LUT, FPGA.

  • References


      [1] Jaiswal MK & Hayden K, “Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division”, IEEE transaction on Circuits and Systems–i: Regular Papers, (2017).

      [2] Singh N, Sasamal TN & Anacan RM, “Design and Synthesis of Goldschmidt Algorithm based Floating Point Divider on FPGA,” IEEE International Conference on Communication and Signal Processing, (2016).

      [3] Ghatte N, Patil S & Bhoir D, “Single Precision Floating Point Division”, Fifth IRF international conference, (2014).

      [4] Huang S, Yu L, Han FJ & Luo Y, “A Pipelined Architecture for User-defined Floating Point Complex Division on FPGA”, IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE), (2017).

      [5] Oberman SF & Flynn M, “Division algorithms and implementation”, IEEE Trans. Comput., (1997).

      [6] Jeong JC, Park WC, Jeong W, Han TD & Lee MK, “A cost-effective pipelined divider with a small lookup table,” IEEE Trans. Comput., (2004).

      [7] Jaiswal MK & Cheung RCC, “High-performance reconfigurable architecture for double precision floating point division”, Proc. 8th Int. Symp. Appl. Reconfigurable Comput. (ARC), Hong Kong, China, (2012), pp. 302–313.


 

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Article ID: 14936
 
DOI: 10.14419/ijet.v7i3.6.14936




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