Conception and Implementation of a BCH Code on a FPGA Board

 
 
 
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    In this paper we have designed and implemented a BCH (15, 7, 5) encoder on FPGA using VHDL description language and we implanted it on an FPGA Spartan 3E Starter board. The digital logic implementation of binary encoding of multiple error correcting BCH code of length n=15 is organized into shift register circuits. Multiple characteristics of cyclic codes will be discussed further on. The results of the simulation and implementation using Xilinx ISE.12.1 software and the LCD screen on the FPGAs Board will be shown at last.


 

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Article ID: 1430
 
DOI: 10.14419/ijet.v2i4.1430




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