Symmetric stacked fast binary counters based on reversible logic

 
 
 
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  • Abstract


    A Symmetric Stacked Fast Binary counter design is proposed in this paper. In the circuit design, the first phase is occupied by 3-bit stacking circuits, which are further followed by combining circuits. The resultant novel circuit thus becomes a 6-bit stacker. A 6:3 counter has been chosen as an example to demonstrate the working of the proposed circuit. The proposed circuit is further implemented by using reversible logic gates. Heat dissipation is a major problem in the designing of a digital circuit. Rolf Landauer has proved that the information loss in a digital circuit is directly proportional to the energy dissipation. The proposed modified Symmetric Stacking counter is implemented using reversible logic gates thus reducing the power dissipation of the circuit.

     


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  • References


      [1] W.D. Pan, M. Nalsaani, "Reversible logic", IEEE Potentials, vol. 24, no. 1, pp. 38-41, 2005. https://doi.org/10.1109/MP.2005.1405801.

      [2] Christopher Fritz, Adly T. Fam, “Fast Binary Counters Based on Symmetric Stacking,” IEEE Trans. on Very Large Scale Integration Systems, vol. 25, issue.10, pp. 2971 - 2975, Jul. 2017. https://doi.org/10.1109/TVLSI.2017.2723475.

      [3] S. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. Electron. Comput. Vol. EC-13, no. 1, pp. 14–17, Feb. 1964. https://doi.org/10.1109/PGEC.1964.263830.

      [4] L. Dadda, “Some schemes for parallel multipliers,” Alta Freq., vol. 34, pp. 349–356, May 1965.

      [5] High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes.

      [6] A Counter-Example to the Mismatched Decoding Converse for Binary-Input Discrete Memoryless Channels.

      [7] A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector.


 

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Article ID: 14141
 
DOI: 10.14419/ijet.v7i4.14141




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