Symmetric stacked fast binary counters based on reversible logic

  • Authors

    • C Santhi research scholar, jjtu
    • Dr. Moparthy Gurunadha Babu
  • Use about five key words or phrases in alphabetical order, Separated by Semicolon.
  • A Symmetric Stacked Fast Binary counter design is proposed in this paper. In the circuit design, the first phase is occupied by 3-bit stacking circuits, which are further followed by combining circuits. The resultant novel circuit thus becomes a 6-bit stacker. A 6:3 counter has been chosen as an example to demonstrate the working of the proposed circuit. The proposed circuit is further implemented by using reversible logic gates. Heat dissipation is a major problem in the designing of a digital circuit. Rolf Landauer has proved that the information loss in a digital circuit is directly proportional to the energy dissipation. The proposed modified Symmetric Stacking counter is implemented using reversible logic gates thus reducing the power dissipation of the circuit.


  • References

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  • How to Cite

    Santhi, C., & Moparthy Gurunadha Babu, D. (2018). Symmetric stacked fast binary counters based on reversible logic. International Journal of Engineering & Technology, 7(4), 2747-2752.