Low leakage SRAM cell for ULP applications
Keywords:SRAM, Low Power, Leakage Current, Fingering, CMOS.
Leakage power is becoming a major concern in battery operated and hand held devices. With the ever reducing size of electronic devices and the use of memory in most of them, the need for low power devices is vastly increasing. These devices are either in active or standby mode of operation. Leakage power in standby mode of operation is of major concern and various methods to minimize it have been proposed at various stages of design cycle. This paper proposes fingering technique that can be used in 6T SRAM cell to reduce leakage power. Leakage power is calculated for 6T SRAM cell designed using two fingers in access transistors and on comparison with conventional 6T SRAM cell, significant reduction in leakage current is obtained. The layout has been designed in UMC 55nm technology using Cadence Virtuoso tool and it has been shown that the leakage power and delay can be reduced.
 S. K. Singh et al., â€˜Analysis of DRV trade-off in deep submicron SRAM for low powerâ€™, WASJ, pp. 56-62, 2014.
 Andrea Calimera et al., â€˜Design techniques and architectures for low leakage SRAMsâ€™, IEEE transactions on circuits and systems, vol. 59, No.9, pp. 1992-2007,Sept. 2012.
 â€˜International technical roadmap for semiconductorsâ€™, 2009 available online at http:// www.itrs.net/links/ 2009ITRS/home2009.htm.
 Eitan N. Shauly, â€˜CMOS leakage and power reduction in transistors and circuits: Process and layout considerationsâ€™, Journal of low power electronics and applications, pp. 1-29, Jan2012.
 Li-Jun Zhang et al., â€˜Leakage power reduction techniques of 55nm SRAM cellsâ€™, IETE Technical Review, Vol. 22, issue 2, pp. 135-145, 2001.
 C.H. Kim et al., â€˜A forward body biased low-leakage SRAM cache: device circuit and architecture considerationsâ€™, IEEE Transactions on VLSI Systems, vol. 13, pp. 349-357, Mar. 2005. https://doi.org/10.1109/TVLSI.2004.842903.
 A. Agarwal et al., â€˜A single-Vt low-leakage gated-ground cache for deep submicronâ€™, IEEE Journal of Solid-State Circuits, vol. 38, pp. 319-328, Feb. 2003. https://doi.org/10.1109/JSSC.2002.807414.
 G. Fukano et al., â€˜A 65nm 1Mb SRAM macro with dynamic voltage scaling in dual power supply scheme for low power SoCsâ€™, International Conference on Memory Technology and Design, Opio, pp. 18-22, May 2008.
 K. Nii et al., â€˜A low power SRAM using auto-backgate-controlled MT-CMOSâ€™, International symposium on low power electronics and design, USA, pp. 293-298, Aug. 1998.
 B. Amelifard et al., â€˜Leakage minimization of SRAM cells in a dual-Vt and dual-Tox technologyâ€™, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, pp. 851-859, July 2008.
 G. Razavipour et al., â€˜Design and Analysis of Two Low-Power SRAM Cell Structuresâ€™, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 10, pp. 1551-1555, Oct. 2009.
 S. P. Vanigalla et al., â€˜To reduce SRAM subthreshold leakage using stack and zig-zag techniquesâ€™, International Journal of Scientific Engineering and Technology, vol1, issue no.2, pp. 51-54, April 2012.
 S. K. Singh et al., â€˜A novel approach to reduce sub threshold leakage in deep sub-micron SRAMâ€™, WASJ, pp. 442-446, 2013.
 J. Park ET. al., â€˜Design of a 22-nm FinFET-Based SRAM with Read Buffer for Near-Threshold Voltage Operationâ€™, IEEE Transactions on Electron Devices, Vol. 62, No. 6, pp. 1698-1704, June 2015. https://doi.org/10.1109/TED.2015.2420681.
 S. Muhammad ET. al., â€˜Eight-FinFET Fully Differential SRAM Cell With Enhanced Read and Write Voltage Marginsâ€™, IEEE Transactions on Electron Devices, Vol. 62, No. 6, pp-2014-2021, June 2015.
 S. K. Singh et al., â€˜An novel approach to reduce leakage current in ULP SRAMâ€™, IETE journal of research, vol.59, issue 6, pp.704-708, Sep. 2014.
 Mansi S warde et al., â€˜Design and analysis of 8X8 static RAMâ€™, IJSER, vol. 6, issue 7, pp. 338-342, Jul. 2015.
 Pavan Kumar bikki et al., â€˜SRAM cell leakage control techniques for ultra-low power applications: A Surveyâ€™, Circuits and systems, pp. 23-52, Feb. 2017.