Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder

  • Abstract
  • Keywords
  • References
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  • Abstract

    A recent years of technology development in Signal processing application a FIR (Finite impulse response) filter design will have a highly compactable with high performance and low power in all digital signal processing application, such as audio processing, signal processing, software define radio and so on. Now a days in our environment will have more signal noises, and fluctuation due to technology development, here the Filter design is mainly configuring the priority to reduce the signal noises and fluctuation in all type of gadgets. In this project, the design contains Transpose form of high performance and high speed filter design using finite impulse response (FIR) filter with technique of pipelined inherently and supported multiple constant multiplication (MCM) in significant with saving power computation. In digital signal processing, the multiplier is a highly required thing, the example of parallel multiplier provide a high-speed and highly reliable method for multiplication, but this parallel multiplier will take large area and also power consumption. In the FIR filter design, multiplier and adders is the maximum priority will take to give the performance, but this MCM multiplier and Adders tree architecture will take large area and maximum power consumption in signal processing. So our Proposed approach of this work, will have replace the MCM multiplier to Truncated Multiplier and using the technique of Truncated based both Signed and Unsigned Operation with SQRT based Carry Select Adder (CSLA), and also replace the normal adders in FIR Filter to SQRT based Carry Select Adder (CSLA). In the proposed system of FIR Filter design results to be analysis with signed and unsigned Truncation using modified technique of HSCG-SCS based SQRT-CSLA and hence proved its more efficient than existing design, such as FIR filter for Truncation multiplier with SQRT-CSLA based Adders, FIR filter for Truncation multiplier with BEC based Adders, FIR filter for Truncation multiplier with RCA, and FIR filter for Truncation multiplier with Common Boolean logic based RCA, and finally implemented this design on VHDL with help of Xilinx FPGA-S6LX9 and shown the performance of proposed design in terms of delay, area, and power.

  • Keywords

    FIR (Finite impulse response), MCM (Multiple Constant Multiplication), CSLA (Carry Select Adder), BEC (Binary Excess Converter), RCA (Ripple Carry Adder), HSCG ( Half-Sum Carry Generation), SCS(Sum Carry Selection).

  • References

      [1] "Low-Power and Area-Efficient Carry Select Adder", B. Ramkumar and Harish M Kittur, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1063-8210/$26.00 © 2011 IEEE.

      [2] "Design and Implementation of 8X8 Truncated Multiplier on FPGA", Suresh R.Rijal (Asst. Prof. KITS, Ramtek), Ms.Sharda G. Mungale (Asst. Prof. PCEA, Nagpur), International Journal of Scientific and Research Publications, Volume 3, Issue 3, March 2013.

      [3] "Area–Delay–Power Efficient Carry-Select Adder", Basant Kumar Mohanty, Senior Member, IEEE, and Sujit Kumar Patel, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 61, NO. 6, JUNE 2014.

      [4] "A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications", Basant Kumar Mohanty, Senior Member, IEEE, and Pramod Kumar Meher, Senior Member, 1063-8210 © 2015 IEEE.

      [5] "High Speed Gate Level Synchronous Full Adder Designs", WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, PADMANABHAN BALASUBRAMANIAN and NIKOS E. MASTORAKIS, Oxford Road, Manchester M13 9PL, UNITED KINGDOM.

      [6] "DESIGN OF ADDER / SUBTRACTOR CIRCUITS BASED ON REVERSIBLE GATES", V.Kamalakannan, Shilpakala.V, Ravi.H.N, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 2, Issue 8, August 2013.

      [7] "Power and Area Efficient Carry Select Adder", 2015 IEEE Recent Advances in Intelligent Computational Systems (RAICS) | 10-12 December 2015 | Trivandrum.

      [8] "An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term", I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang Peng, Proceedings of the International Multi Conference of Engineers and Computer Science 2012 Vol II.

      [9] "Designing Efficient Online Testable Reversible Adders With New Reversible Gate", HimanshuThapliyal and A.P Vinod School of Computer Engineering, Nanyang Technological University, Singapore, 2007 IEEE.

      [10] "Variable Truncated Multiplier with Low Power", AthiraPrasad , Robin Abraham, International Journal Of Engineering And Computer Science ISSN:2319-7242.

      [11] "Design and implementation of truncated multipliers for precision improvement", 2013 International Conference on Computer Communication and Informatics (ICCCI -2013), Jan. 04 – 06, 2013, Coimbatore, INDIA.

      [12] "On The Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays", Theo Drane, Thomas Rose and George A. Constantinides, 2013, IEEE TRANSACTIONS ON COMPUTERS.

      [13] "Design of Reversible Adders Using A Novel Reversible BKG Gate", Bhuvana B, KanchanaBhaaskaran V S, 2016 Online International Conference on Green Engineering and Technologies (IC-GET).

      [14] "A Novel Design of Compact Reversible SG Gate and its Applications", Payal Garg, Sandeep Saini, 2014 International Symposium on Communications and Information Technologies (ISCIT).

      [15] SivakumarV.G.and RajendranV.(2013), “Comparison and analysis of verticalcoherenceintheshallowwateroftwooceanregion”,AmericanJournalofAppliedSciencesVol. 10 No.6 542-548/ Apr-May2013.

      [16] Romana Yousuf, Najeeb-ud-din,“Synthesis of Carry Select Adder in 65 nm FPGA”, IEEE.

      [17] Animulislam, M.W. Akram, S.D. pable, Mohd. Hasan, “Design and Analysis of Robust Dual Threshold CMOS Full Adder Circuit in 32 nm Technology”, International Conference on Advanced in Recent Technologies in Communication and Computing, 2010.

      [18] V. Kantabutra, “Accelerated two-level carry-skip adders-a type of very fast adders,” IEEE Transactions on Computers, vol. 42, no. 11, pp. 1389–1393, 1993.

      [19] K. Chirca, M. Schulte, J. Glossner, et al., “A static low-power, high-performance 32-bit carry skip adder,” in Proceedingsof the EUROMICRO Symposium on Digital System Design (DSD ’04), pp. 615–619, Rennes, France, August-September 2004.

      [20] K. Chircaet al., “A static low-power, high-performance 32-bit carry skip adder,” in Proc. EuromicroSymp. Digit. Syst. Design (DSD), Aug./Sep. 2004, pp. 615–619.

      [21] V. G. Oklobdzija, B. R. Zeydel, H. Dao, S. Mathew, and R. Krishnamurthy, “Energy-delay estimation technique for highperformance microprocessor VLSI adders,” in Proc. 16th IEEE Symp. Comput. Arithmetic, Jun. 2003, pp. 272–279.

      [22] R. Zlatanovici, S. Kao, and B. Nikolic, “Energy–delay optimization of 64-bit carry-lookahead adders with a 240 ps 90 nm CMOS design example,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 569–583, Feb. 2009.




Article ID: 13519
DOI: 10.14419/ijet.v7i2.32.13519

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