FPGA implementation of 1000base-x Ethernet physical layer core

  • Abstract
  • Keywords
  • References
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  • Abstract

    This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.



  • Keywords

    Giga Ethernet;virtex6 FPGA;PHY; PCS; PMA;8B/10B Coding; Synchronization; PISO; SIPO.

  • References

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Article ID: 13469
DOI: 10.14419/ijet.v7i4.13469

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