FPGA implementation of 1000base-x Ethernet physical layer core

 
 
 
  • Abstract
  • Keywords
  • References
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  • Abstract


    This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.

     

     


  • Keywords


    Giga Ethernet;virtex6 FPGA;PHY; PCS; PMA;8B/10B Coding; Synchronization; PISO; SIPO.

  • References


      [1] P. Nallani, Mr. T. Vasudeva Reddy, M. Tech, Embedded systems, BVRIT, E.C.E Dept, Hyderabad, India,” FPGA Implementation of Low Power Serial to High Speed Data Networks”, International Journal on Recent and Innovation Trends in Computing and Communication, Volume: 2 Issue: 8, ISSN: 2321-81692377 – 2383, August 2014.

      [2] K. Azadet, E. Haratsch, “DSP implementation issues in 1000BASE-T Gigabit Ethernet”, IEEE, Taiwan, 07 August 2002.

      [3] V.R. Gad, R. S. Gad and G.M. Naik, Department of Electronics, Goa University, Goa, India, ”IMPLEMENTATION OF GIGABIT ETHERNETSTANDARD USING FPGA”, International Journal of Mobile Network Communications & Telematics (IJMNCT) Vol.2, No.4, August 2012.

      [4] S.L. Chew, M. Hassoun, “Implementation, verification and synthesis of the Gigabit Ethernet 1000BASE-T physical coding sublayer“, Conference: Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on, Volume: 2, February 2001.

      [5] S. Venkata Kishore, M.Srilatha, Mr.Y.S.Chakrapani, ECE Department, Gudlavalleru, Krishna District, Andhra Pradesh -521356, India,“ Design and Implementation of High Speed Data Transmission over Dual Independent Aurora Channels on One GTX dual tile usingVirtex-5 FPGA”, International Journal of Scientific & Engineering Research, Volume 4, Issue 12, December-2013 1552, ISSN 2229-5518, 2013.

      [6] M.Maadi, Middle East Technical University, Department of Electrical and Electronics Engineering, 06531, Ankara, Turkey,”An 8b/10b Encoding Serializer/Deserializer (SerDes) Circuit for High Speed Communication Applications Using a DC Balanced, Partitioned Block, 8b/10b Transmission Code”, International Journal of Electronics and Electrical Engineering Vol. 3, No. 2, April, 2015.

      [7] P. kJana, D. p. Acharya, Department of ECE, National Institute of Technology, Rourkela, ”Coverage Analysis in the Verification of 8B/10B Encoder” ,published by International Journal of Computer Applications® (IJCA),International Symposium on Devices MEMS, Intelligent Systems & Communication (ISDMISC) 2011.

      [8] K. Sahni, K. Rawat, S. Pandey, Z. Ahmad, Amity University , Noida, Uttar Pradesh, ”Low Power Approach for Implementation of 8B/10B Encoder and 10B/8B Decoder Used for High Speed Communication”,IEEE 2014.

      [9] Forouzan, fourth edition, “Data comuunications and networking”.

      [10] H. Ashrafi, M.Mousazadeh, K.Hadidi, Microelectronics Research Center, Urmia University, Urmia – Iran,” An 8B/10B Encoder With 2GHz Operating Frequency”, IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 October 2016, Abu Dhabi, UAE,2016.

      [11] University of New Hampshire InterOperability Laboratory,” GIGABITETHERNET Clause 36 Physical Coding Sublayer (PCS) Test Suite Version 2.1”, February 03, 2006.

      [12] J. Huang, R. Spencer, Solid-State Circuits Research Laboratory, Department of Electrical and Computer Engineering, University of California, Davis, ”Simulated Performance of 1000BASE-T Receiver with Different Analog Front End Designs”, published in the Proceedings of the 35th Asilomar Conference on Signals, Systems, and Computers, 2001.

      [13] S. Samanta, A. Dastidar, Dept. of Electronics and Communication Engg, Center for Advanced Post Graduate Studies, BPUT, Odisha, Rourkela,” Implementation of 10bit SerDes for Gigabit Ethernet PHY”, International Conference on Man and Machine Interfacing (MAMI), 2015.


 

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Article ID: 13469
 
DOI: 10.14419/ijet.v7i4.13469




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