Design of high speed Wallace tree multiplier using 8-2 and 4-2 adder compressors


  • K Jayaram Kumar GIET(A), RAJAHMUNDRY
  • Dr. T. V. Prasad GIET(A), RAJAHMUNDRY





Wallace Tree Multiplier, Compressors and Adders.


Multiplication is one of the most common arithmetic operations employed in digital systems such as FIR filters and DSP processors but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improv-ing the efficiency of the circuit. High-speed multiplier which uses the high-speed adder is designed based on the Wallace tree concept in this paper. In this paper first we present an approach towards the reduction of delay in Wallace tree multipliers by using 8:2 and 4:2 adder com-pressors, in the partial product reduction stage. The proposed design is also compared to the Wallace Tree multiplier which uses 4:2 and 8:2 adder compressors in terms of propagation delay. The proposed design enhances speed of the system by 74.1% compared to the conven-tional Wallace Tree multiplier, while 24.1 % reduction was achieved in the delay of the system relative to Wallace tree multiplier with 16-bit adder with one of the 8-2 adder compressors.




[1] S. Akhter and S. Chaturvedi, "HDL based implementation of n x n bit serial multiplier", Proc. of 2014 IEEE Int. Conf. on Sig. Processing and Integrated Networks (SPIN), pp. 470-474, 2014.

[2] S. Shah, A. AI-Khalili, and D. AI-Khalili, "Comparison of 32-bit Multipliers for Various Performance Measuresâ€, Proc. of the 12th Int. Conf. on Microelectronics, ICM 2000, 2000.

[3] V. Sindhu and R. Kumar, "Analysis Simulation and Comparison of Different Multiplier Algorithmsâ€, Int. J. of Management, IT and Engg. Vol. I, No. 3, pp. 146-156, 2011.

[4] Rajaram, Srinath, and K. Vanithamani, "Improvement of Wallace Multipliers using Parallel Prefix Adders", Proc. of 2011 Int. Conf. on Sig. Processing, Comm., Computing and Networking Technologies (ICSCCN), pp. 781-784. IEEE, 2011.

[5] Vinoth, C., VS Kanchana Bhaaskaran, B. Brindha, S. Sakthikumaran, V. Kavinilavu, B. Bhaskar, M. Kanagasabapathy, and B. Sharath. "A Novel Low Power and High Speed Wallace Tree Multiplier for RISC Processor", Proc. of 3rd Int. Conf. on Electronics Computer Tech. (ICECT 2011), Vol. 1, pp. 330-334, IEEE, 2011.

[6] V. Gupta, D. Mohapatra, S. P. Park, A. Raghunathan, and K. Roy, “IMPACT: IMPrecise adders for Low-Power Approximate Computingâ€, Proc. of Int. Symp. on Low Power Electronics and Design (ISLPED). 1-3 Aug. 2011.

[7] S. Cheemalavagu, P. Korkmaz, K.V. Palem, B.E.S. Akgul, and L.N. Chakrapani, “A Probabilistic CMOS Switch and its Realization by Exploiting Noise,†in Proc. IFIP-VLSI SoC, Perth, Australia, Oct 2005.

[8] H.R. Mahdiani, A. Ahmadi, S.M. Fakhraie, C. Lucas, “Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applicationsâ€, IEEE Trans. on Circuits and Systems I: Regular Papers, Vol. 57, No. 4, pp. 850-862, April 2010.

[9] S.K. Sangjin, S. Hong, M.C. Papaefthymiou and E. Stark, “Low Parallel Multiplier design for DSP Applications through Coefficient Optimizationâ€, Int. ASIC/SOC Conf., pp.286-290, 1999.

[10] V. Gupta, D. Mohapata, S.P. Park, A. Raghunathan and K. Roy, “IMAPCT: IM precise adder for low-power approximate and computingâ€, Proc. of Int. Symp. on Low Power Electronics and Design (ISLED), pp. 409-414, 2011.

[11] A.B. Kahng and S. Kang, “Accuracy-configurable adder for Approximate Arithmetic Designâ€, Proc. of Design Automatic Conf. (DAC), pp. 820-825, 2012.

[12] D. Shin and S. Kunita, “Approximate logic synthesis for error tolerance applicationsâ€, Proc. of Design, Automatic and Test in Europe Conf. and Exhibition (DATE), pp. 957-960, 2010.

[13] Anju, S., and Saravanan, M., “High Performance Dadda Multiplier Implementation Using High Speed Carry Select Adderâ€, Int. J. of Adv. Res. in Computer and Comm. Engg., 2(3), 2013.

[14] Wang, Z., Jullien, G. A., and Miller, W. C., “A New Design Technique for Column Compression Multipliersâ€, IEEE Trans. on Computers, 44(8), pp. 962-970, 1995.

[15] Anitha, P., and Ramanathan, P., “A New Hybrid Multiplier using Dadda and Wallace Methodâ€, Proc. of Int. Conf. on Electronics and Comm. Systems (ICECS), pp. 1-4, IEEE, 2014.

[16] Chu, W., Unwala, A. I., Wu, P., and Swartzlander, E. E., “Implementation of a High Speed Multiplier using Carry Look-Ahead Addersâ€, Proc. of Asilomar Conf. on Signals, Systems and Computers (pp. 400-404). IEEE, 2013.

[17] Samundiswary, P., Anitha, K., “Design and Analysis of CMOS Based DADDA Multiplierâ€, Int. J. of Comp. Engg. and Management IJCEM, 1(16), 12-17, 2013.

[18] V. G. Oklobdzija, D. Villeger,"Improving Multiplier Design by using Improved Column Compression Tree optimized Final Adder in CMOS technology", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 3, Issue-2, pp 292-301, 1982.

[19] M. Rouholamini, O. Kavehie, A.-P. Mirbaha, S. J. Jasbi, and K. Navi, “A new design for 7:2 compressors,†Proc. IEEE/ACS Int. Conf. Comput. Syst. Appl. (AICCSA), Amman, Jordan, May 2007, pp. 474–478.

[20] J. S. Altermann, E. A. C. da Costa, and S. Bampi, “Fast Forward and Inverse Transforms for the H.264/AVC Standard using Hierarchical Adder Compressors,†in Proc. IEEE/IFIP Int. Conf. VLSI Syst. Chip (VLSI-SoC), Madrid, Spain, pp. 310–315, Sep. 2010.

[21] C.S. Wallace, “A suggestion for a fast multiplierâ€, IEEE Transactions on Electronics, pp 14-17, 1964.

[22] Chia Hao Cin Lin, Ing-Chao lin, â€High Accuracy Approximate Multiplier with Error Correctionâ€, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, pp 33-38, 2013.

[23] A Momeni and F. Lombardi,†Design and Analysis of Approximate Compressors for Multiplicationâ€, IEEE Trans. on Computers, pp 1-11, 2015

[24] Guyot, B. Hochet, and J. Muller, "A Way to Build Efficient Carry Skip Adders, " IEEE Trans. on Computers, Vol. 36, No. 10, pp. 1144--1152, 1987.

[25] M. Ortiz, F. Quiles, J. Hormigo, F. J. Jaime, J. Villalba, and E. L. Zapata, "Efficient Implementation of Carry-Save Adders in FPGAs", Proc. of 20th IEEE Int. Conf. on App. Specific Systems, Architectures and Processors (ASAP 2009), IEEE, pp. 207-210, 2009

[26] R. Uma, V. Vijayan, M. Mohanapriya, and S. Paul, "Area, Delay and Power Comparison of Adder Topologies," Int. J. of VLSI and Communication Systems, vol. 254, 2012.

[27] B. Ramkumar and H. M. Kittur, "Low-power and area-efficient carry select adder, " Very Large Scale Integration (VLSl) Systems, IEEE Transactions on, vol. 20, no. 2, pp. 371-375, 2012.

[28] Joao S. Altermann, Eduardo A. C. da Costa and Sergio Bampi, "Fast Forward and Inverse Transforms for the H.264/AVC Standard Using Hierarchical Adder Compressors", IEEE Trans. on Very Large Scale Integration (VLSl) Systems, pp. 310-315, 2010.

[29] Bianca Silveira, Guilherme Paim, Cláudio Machado Dinizand and Sergio Bampi, "Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design", IEEE Trans. on Circuits and Systems–I, pp. 1-12, 2017.

[30] S. Rajaram and Mrs. K. Vanithamani, “Improvement of Wallace Tree Multipliers using Parallel Prefix Addersâ€, Proc. of 2011 Int. Conf. on Sig. Processing, Comm., Computing and Networking Technologies (ICSCCN 2011), 2011.

[31] Raiyyan E Masumdar, "Design of high performance Wallace Tree Multiplier using Compressors and Parallel Prefix Adders," Int. J. of Electrical, Electronics and Data Comm., Vol. 4, 2016.

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