A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array

 
 
 
  • Abstract
  • Keywords
  • References
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  • Abstract


    A novel idea of 8-Transistor (8T) static random access memory cell with enhanced information stability, sub threshold operation may be outlined. Those prescribed novel built single-ended for dynamic control 8 transistors static RAM (SRAM) cell enhances the static noise margin (SNM) to grater low energy supply. The suggested 8T takes less read and write power supply compared to 6T. Those suggested 8T need higher static noise margin than that from 6T. The portable microprocessor chips need ultralow energy consuming circuits on use battery to more drawn out span. The power utilization might be minimized utilizing non-conventional gadget structures, new circuit topologies, and upgrading the architecture. Although, voltage scaling require of the operation completed over sub threshold for low power consumption, and there will be an inconvenience from exponential decrease in execution. However, to sub threshold regime, that data stability of SRAM cell might a chance to be a amazing issue and worsens for those scaling from claming MOSFET ought to sub-nanometer engineering technology.

     

     

  • Keywords


    8-Transistor (8T) static RAM, Static noise margin, ultralow voltage (ULV), dynamic feedback

  • References


      [1] K. Takeda et al., “A read-static-noise-margin-free SRAM cell for low VDD and high-speed applications,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 113–121, Jan. 2006.

      [2] Keerthi, Rajasekhar M.S.E., Department of Electrical Engineering, Wright State University, 2007, Stability and Static Noise Margin Analysis of Static Random Access Memory

      [3] Debasis Mukherjee1, Hemanta Kr. Mondal and B.V.R. Reddy ‘Static Noise Margin Analysis of SRAM Cell for High Speed Application’ IJCSI International Journal of Computer Science Issues, Vol. 7, Issue 5, September 2010

      [4] C. Kushwah and S. K. Vishvakarma, “Ultra-low power sub-threshold SRAM cell design to improve read static noise margin,” in Progress in VLSI Design and Test (Lecture Notes in Computer Science), vol. 7373. Berlin, Germany: Springer-Verlag, 2012, pp. 139–146.

      [5] B. H. Calhoun and A. P. Chandrakasan, “A 256-kb 65-nm sub-threshold SRAM design for ultra- low-voltage operation,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 680–688, Mar. 2007

      [6] M.-H. Tu, J.-Y. Lin, M.-C. Tsai, S. J. Jou, and C.-T. Chuang, “Single ended sub threshold SRAM with asymmetrical write/read-assist,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 12, pp. 3039–3047, Dec. 2010

      [7] K. Roy and S. Prasad, Low-Power CMOS VLSI Circuit Design, 1st ed. New York, NY, USA: Wiley, 2000.

      [8] C. B. Kushwah and S. K. Vishvakarma, “A sub-threshold eight transistor (8T) SRAM cell design for stability improvement,” in Proc. IEEE Int. Conf. IC Design Technol. (ICICDT), May 2014, pp. 1–4.

      [9] N. Verma and A. P. Chandrakasan, “A 256 kb 65 nm 8T sub threshold SRAM employing sense- amplifier redundancy,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141–149, Jan. 2008.


 

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Article ID: 12185
 
DOI: 10.14419/ijet.v7i2.20.12185




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