Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

  • Authors

    • Anshu Gupta
    • Lalita Gupta
    • R K. Baghel
    2018-04-12
    https://doi.org/10.14419/ijet.v7i2.16.11413
  • Continuous time sigma delta modulator SDM/DSM, analog to digital converter, CMOS process, three stage OTA, Sub threshold, integrator, dynamic standard comparator, two tail transistors, Low power circuit, digital-to-analog converter, oversampling converte

  • A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator.  We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/   and with low power consumption of 296.72nW.  A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

  • References

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    Gupta, A., Gupta, L., & K. Baghel, R. (2018). Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator. International Journal of Engineering & Technology, 7(2.16), 38-51. https://doi.org/10.14419/ijet.v7i2.16.11413