Design of high performance, low power sub thresholds ram using source coupled logic for implantable applications.

  • Abstract
  • Keywords
  • References
  • PDF
  • Abstract

    Low power circuits functioning in sub threshold were proposed in earlier seventies. Recently, growing with the need of low power consumption, the low power circuits have became more attractive. However, the act of sub threshold design logics has become sensitive to the supply voltage & process variations like temperature and so on. In sub threshold region of operations the supply voltage (Vgs) is less than the threshold (Vth).This leads to less power dissipation in over all circuit, but drastically increment in propagation delay. The major intention of the paper is to offer new low power & less delay digital circuits. SRAM is the major power drawing element and dissipation is about 40% in total power. The primary objective is to design of sub threshold SRAM design, Functionality and performance is estimated from the power and delay.The second objective is to offer novel Source coupled logic based SRAM (ST-SC SRA) M & Operating these design under sub threshold operating region. Performance is analyzed through power and delay. Finally comparing the traditional sub threshold SRAM with source coupled based SRAM in power and delay on par with the performance. Discussing some of the applications, where there is a requirement of less power and delay.


  • Keywords

    St-SC Sram; Sub-Threshold Sram; EEG; ECG; Pace -Makers

  • References

      [1] H. N. Patel, F. B. Yahya and B. H. Calhoun, "Sub threshold SRAM: Challenges, design decisions, and solutions, pp. 321-324, (2017).

      [2] N. Zheng and P. Mazumder, "Modeling and Mitigation of Static Noise Margin Variation in Sub threshold SRAM Cells, pp. 2726-2736, 2017.

      [3] Yasuhisa Omura, Abhijit Mallik, and Naoto Matsuo: Performance Prospects of Sub threshold Logic Circuits by MOS Devices for Low-Voltage and Low-Energy Applications, First Edition (2017).

      [4] C. B. Kushwah and S. K. Vishvakarma, "A Single-Ended With Dynamic Feedback Control 8T Sub threshold SRAM Cell," vol. 24, no. 1, pp. 373-377, Jan. (2016)

      [5] P. Sharma, R. Anusha, K. Bharath, J. K. Gulati, P. K. Walia and S. J. Darak, "Quantification of figures of merit of 7T and 8T SRAM cells in sub threshold region and their comparison with the conventional 6T SRAM cell, pp. 1-2. (2016)

      [6] P. Sreelakshmi, K. S. Pande and N. S. Murty, "SRAM cell with improved stability and reduced leakage current for sub threshold region of operation, pp. 1-5. (2015)

      [7] S. Basuta and M. Shams, "Single-ended 6T sub-threshold SRAM with horizontal local bit-lines, pp. 1-4. 2015

      [8] F. Moradi and J. K. Madsen, "Improved read and write margins using a novel 8T-SRAM cell. pp. 1-5(2014)

      [9] B. Ebrahimi, H. Afzali-Kusha and A. Afzali-Kush: Low power and robust 8T/10T sub threshold SRAM cell pp.141- 144(2012).

      [10] Kanika Kaur and arti noor : strategies & methodologies for low power VLSI designs: a review in International Journal of Advances in Engineering & Technology..159-165. (2011).

      [11] S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid- Pecht and A. Fish : Digital sub threshold logic design - motivation and challenges pp.702-706.(2008)

      [12] Ramesh Vaddi, S Dasgupta, RP Agarwal: Device and circuit co-design robustness studies in the sub threshold logic for ultra-low-power applications for 32 nm CMOS, (2010).

      [13] Babayan-Mashhadi and S. Mortazavi, "A novel ultra-low- power time-domain comparator based on sub threshold source-coupled logic. pp. 471-475. (2017)

      [14] Sumit Vyas and Sanjeev Rai: A Survey on Power-Delay Reduction Techniques for Ultra-Low-Power Sub threshold SCL Circuits (2012).

      [15] A. Tajalli and Y. Leblebici, "Sub threshold SCL for ultra- low-power SRAM and low-activity-rate digital systems, pp. 164-167. (2009).




Article ID: 11280
DOI: 10.14419/ijet.v7i2.12.11280

Copyright © 2012-2015 Science Publishing Corporation Inc. All rights reserved.