Optimization of Physically-Aware Synthesis for Digital Implementation Flow

 
 
 
  • Abstract
  • Keywords
  • References
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  • Abstract


    Synthesis is very important to have a high-quality implementation of every design. However, more accurate results could not be achieved if we will not consider the expected effects of routing delay introduced by placement and routing. This delay causes the poor timing correlation between the logical-only synthesis and Place and Route. . Now, tools with physical aware synthesis allow the user to integrate the physical information much early in the process. While such technique is readily available in the tools itself, there is no established flow to utilize the use of physical aware synthesis to the whole ASIC design process. Moreover, there’s lack of in-depth experimental analysis, specifically on commercially available designs, on the correlation of physically aware synthesis to the subsequent steps in the backend of the whole design process such as the place and route (PnR) and Timing Closure (STA). With this study, optimal flow for synthesis run is achieved through several experimental setups. Effects in place and route (PNR), and Static Timing Analysis (STA) is also observed and documented. Two different physically aware synthesis methodologies are proven to have improved timing correlation between the synthesis and PNR results. Power after signoff also improved significantly. Total runtime from synthesis to timing closure reduces because of much lesser violations in the first iteration alone.

     

     


  • Keywords


    Physically-aware Synthesis; synthesis; PAM; PAS; PLE

  • References


      [1] Balasubramanian J., “Making FPGA Synthesis Physically Aware”, Retrieved from http://chipdesignmag.com/display.php?articleId=1002, November 2015.

      [2] Alpert, C.J., Karandikar, S.K., Zhuo Li ; Gi-Joon Nam, et.al. (2007), Techniques for Fast Physical Synthesis. Proceedings of the IEEE 95, 573-599.

      [3] Papa, D., Moffitt, M.D., Alpert, C.J., Markov, I.L. (2010), Speeding Up Physical Synthesis with Transactional Timing Analysis. IEEE Design and Test of Computers 27, 14-25.

      [4] Parimi N. (2015), Leveraging Physically Aware Design-for-Test to Improve Area, Power, and Timing. Cadence Designs Systems.

      [5] Weste, N., Harris, D., & Banerjee, A. (2005), CMOS VLSI design. A circuits and systems perspective 11, 739.

      [6] Franzon, P.D., “ASIC Design Flow”, Advance VLSI Design. Retrieved from www.ece.ncsu.edu/erl/faculty/paulf.html, 2012

      [7] Genus Physical User Guide. Genus Synthesis Solution. Cadence Design Systems, Inc., Seely Avenue, San Jose, CA 95134, USA., 2015

      [8] Zeidman, Bob., “Back to the basics: Programmable Systems on a Chip”, Zeidman Technologies, Retrieved from http://www.design-reuse.com/articles/10991/back-to-the-basics-programmable-systems-on-a-chip.html , 2005

      [9] Moxon T., “Exploring New Design Flows”, Retrieved from http://www.eetimes.com/document.asp?doc_id=1216162, 2001

      [10] Journal on Demand, “Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation”, EE Journal, Retrieved from http://www.eejournal.com/archives/on-demand/2014060304-cadence-synthesis/, 2016.

      [11] Kudva Gopi, “Using Physically Aware Synthesis Techniques to Speed Design Closure of Advanced-Node SoCs” Retrieved from http://chipdesignmag.com/sld/blog/2015/03/23/using-physically-aware-synthesis-techniques-to-speed-design-closure-of-advanced-node-socs/, November 2015.

      [12] Starter Guide SYN + DFT MDK. Lattice Semiconductors Corp., Oregon, United States, 2015.

      [13] Tasuoka M, Watanabe R., Otsuka T., and Hasegawa T. (2015), Physically aware high level synthesis design flow. In 52nd Annual Design Automation Conference, pp. 1-6.

      [14] Lin Zhong, N.K. Jha, “Interconnect-aware High-level Synthesis for Low Power”. In IEEE/ACM International Conference on Computer Aided Design, pp 110-117.

      [15] Pandini, D., Pileggi, L., & Strojwas, A. (2002), Congestion-aware Logic Synthesis. In Conference on Design, automation and test in Europe, pp. 664.

      [16] Clarke, M., Hammerschlag, D., Rardon, M., & Sood, A. (2011). Eliminating routing congestion issues with logic synthesis. Whitepaper, Cadence Design Systems., Retrieved from http://www.cadence.com/rl/resources/white_papers/routin g_congestion_wp.pdf, December 2016

      [17] Wu, J., Ma, C., & Huang, B. (2008). Congestion Aware High Level Synthesis Combined with Floorplanning. In Pacific-Asia Workshop on Computational Intelligence and Industrial Application, Vol. 2, pp. 935-938.


 

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Article ID: 11002
 
DOI: 10.14419/ijet.v7i2.11.11002




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