Low power and high speed GDI based convolution using Vedic multiplier

  • Authors

    • C Priyanka
    • N Manoj Kumar
    • L Sai Priya
    • B Vaishnavi
    • M Rama Krishna
    2018-03-18
    https://doi.org/10.14419/ijet.v7i2.7.10934
  • Linear convolution, CMOS, GDI, Adders, Vedic multiplier.
  • Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system.  Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system.  Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology.

     

  • References

    1. [1] Arkadiy Morgenshtein , “Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits Ieee Transactions Vol-10,No-5,Oct-2002.

      [2] N. Weste and K. Eshraghian, Principles of CMOS digital de- sign. Reading, MA: Addison-Wesley, pp. 304–307.

      [3] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low- powerCMOS digital design,†IEEE J. Solid-State Circuits, vol. 27, pp.473–484, Apr. 1992.

      [4] A. P. Chandrakasan and R. W. Brodersen, “Minimizing power consump- tion in digital CMOS circuits,†Proc. IEEE, vol. 83, pp. 498–523, Apr.1995.

      [5] W. Al-Assadi, A. P. Jayasumana, and Y. K. Malaiya, “Pass-transistor logic design,†Int. J. Electron., vol. 70, pp. 739–749, 1991.

      [6]

      Pierre, John W. â€A novel method for calculating the convolution sum of two finite length sequences.†Education, IEEE Transactions on 39.1(1996): 77-80.

      [7] Jain, S. ; Saini S. “High Speed Convolution and Deconvolution algorithm (Based on Ancient Indian Vedic Mathematics) electricalengineering/electronics, computer, telecommunications and information technology (ecti-con), 2014 11th international conference on doi: 10.1109/ecticon.2014.6839756 Publication Year: 2014 , Page(s): 1 – 5.IEEE 2014

      [8] Lomte, Rashmi K., and P. C. Bhaskar. â€High Speed Convolution and Deconvolution Using Urdhva Triyagbhyam.†VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on. IEEE, 2011.

      [9] Itawadiya, Akhalesh K., et al. â€Design a DSP operations using vedic mathematics.†Communications and Signal Processing (ICCSP), 2013 International Conference on. IEEE, 2013.

      [10] Bansal, Y. ; Madhu, C. ; Kaur, P.†High speed Vedic Multiplier Design A Review†Proceedings of 2014 RAECS UIET Panjab UniversityChandigarh, 06 – 08.IEEE March, 2014

      [11] Huddar S., Kalpana M., Mohan S.â€Novel High SpeedVedic Mathematics Multiplier Using Compressors†Automation, Computing,Communication, Control and Compressed Sensing (iMac4s), 2013 International Multi-Conference pp: 465 – 469

      [12] Senapati, Ratiranjan, Bandan Kumar Bhoi, and Manoranjan Pradhan†Novel binary divider architecture for high speed VLSI applications.†Information & Communication Technologies (ICT), 2013 IEEE Conference on. IEEE, 2013.

      [13] BALA DASTAGIRI, N. and HARI KISHORE, K., 2016. Analysis of low power low kickback noise dynamic comparators in pacemakers. Indian Journal of Science and Technology, 9(44),..

      [14] BALA DASTAGIRI, N. and HARI KISHORE, K., 2016. Reduction of kickback noise in latched comparators for cardiac IMDs. Indian Journal of Science and Technology, 9(43),.),

      [15] HUSSAIN, S.N. and KISHORE, K.H., 2016. Computational Optimization of Placement and Routing using Genetic Algorithm. Indian Journal of Science and Technology, 9(47),.

      [16] MUDAVATH, M. and HARIKISHORE, K., 2016. Design of CMOS RF front-end of low noise amplifier for LTE system applications. Asian Journal of Information Technology, 15(20), pp. 4040-4047.

      [17] MURALI, A., KAKARLA, H.K. and VENKAT REDDY, D., 2016. Integrating FPGAs with trigger circuitry core system insertions for observability in debugging process. Journal of Engineering and Applied Sciences, 11(12), pp. 2643-2650

      [18] BALA GOPAL, P., HARI KISHORE, K., KALYANA VENKATESH, R.R. and HARINATH MANDALAPU, P., 2015. An FPGA implementation of onchip UART testing with BIST techniques. International Journal of Applied Engineering Research, 10(14), pp. 34047-34051

      [19] BHARADWAJ, M. and KISHORE, H., 2017. Enhanced launch-off-capture testing using BIST design. Journal of Engineering and Applied Sciences, 12(3), pp. 636-643.

      [20] VUNDAVILLI, P.R., PARAPPAGOUDAR, M.B., KODALI, S.P. and BENGULURI, S., 2012. Fuzzy logic-based expert system for prediction of depth of cut in abrasive water jet machining process. Knowledge-Based Systems, 27, pp. 456-464.

      [21] KILARU, S., HARIKISHORE, K., SRAVANI, T., ANVESH CHOWDARY, L. and BALAJI, T., 2014. Review and analysis of promising technologies with respect to Fifth generation networks, 1st International Conference on Networks and Soft Computing, ICNSC 2014 - Proceedings 2014, pp. 248-251

  • Downloads

  • How to Cite

    Priyanka, C., Manoj Kumar, N., Sai Priya, L., Vaishnavi, B., & Rama Krishna, M. (2018). Low power and high speed GDI based convolution using Vedic multiplier. International Journal of Engineering & Technology, 7(2.7), 733-738. https://doi.org/10.14419/ijet.v7i2.7.10934