A novel design of high performance1-bit adder circuit at deep sub-micron technology
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2017-12-21 https://doi.org/10.14419/ijet.v7i1.1.10822 -
Hybrid logic, Power Consumption, Delay, Transistor Count, PDP. -
Abstract
In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-bit full adders. Also the number of transistors has been reduced to 13 where as the existiing hybrid full adder circuit has 16 transistors. The proposed circuit was implemented using mentor graphics tool in 45nm, 32nm and 22nm technologies with different supply voltages.
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References
[1] C.-K. Tung, Y.-C. Hung, S.-H. Shieh, and G.-S. Huang, “A low-power high-speed hybrid CMOS full adder for embedded system,†in Proc. IEEE Conf. Design Diagnostics Electron. Circuits Syst., vol. 13. Apr. 2007, pp. 1–4.
[2] S. Goel, A. Kumar, and M. A. Bayoumi, “Design of robust, energyefficient full adders for deep-submicrometer design using hybrid-CMOS logic style,†IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 1309–1321, Dec. 2006.
[3] T. Venkata Rao and A. Srinivasulu, “Modified level restorers using current sink and current source inverter structures for BBL-PT full adder†, Radioengineering, vol. 21, no. 4, pp. 1279– 1286, 2012.
[4] N. H. E. Weste, D. Harris, and A. Banerjee, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd ed. Delhi, India: Pearson Education, 2006.
[5] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Delhi, India: Pearson Education, 2003.
[6] D. Radhakrishnan, “Low-voltage low-power CMOS full adder,†IEE Proc.-Circuits Devices Syst., vol. 148, no. 1, pp. 19–24, Feb. 2001.
[7] T V Rao and Avireni Srinivasulu“16-BIT RCA Implementation Using Current Sink Restorer Structure†IJDATICS, Vol. 4, No. 1, pp.9-14, December 2013.
[8] R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,†IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079–1090, Jul. 1997.
[9] C. H. Chang, J. M. Gu, and M. Zhang, “A review of 0.18-μm full adder performances for tree structured arithmetic circuits,†IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686–695, Jun. 2005.
[10] T. Venkata Rao et al, “Design and Implementation of 1-Bit Full Adder Using Voltage Bootstrapping Circuitâ€, International Journal of pure and Applied Mathematics, Vol. 117, No. 18, pp.367-372, 2017.
[11] M. Shams, T. K. Darwish, and M. A. Bayoumi, “Performance analysis of low-power 1-bit CMOS full adder cells,†IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp. 20–29, Feb. 2002.
[12] P. Balakrishna et al, “Low Static Power Consumption and High Performance 16-Bit Ripple Carry Adder Implementation by Using BBL-PT Logic styleâ€, International Journal of Applied Engineering Research, Vol. 9, Number 23, pp. 22727-22741, 2014.
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How to Cite
Rao Tirumalasetty, V., V. Mohan Krishna, C., Sai Sree Tanmaie, K., Lakshmi Naveena, T., & Jonathan, C. (2017). A novel design of high performance1-bit adder circuit at deep sub-micron technology. International Journal of Engineering & Technology, 7(1.1), 660-663. https://doi.org/10.14419/ijet.v7i1.1.10822Received date: 2018-03-30
Accepted date: 2018-03-30
Published date: 2017-12-21