A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

 
 
 
  • Abstract
  • Keywords
  • References
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  • Abstract


    This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to- Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non- binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv. Step which is comparable with existing ADC topologies.


  • Keywords


    Successive Approximation Register Analog-to-Digital Converter; ENOB; INL; DNL; Cardiac Implantable Medical Device; Comparator.

  • References


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Article ID: 10319
 
DOI: 10.14419/ijet.v7i2.8.10319




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