Implementation of MHLFF based low power pulse triggered flip flop
Keywords:Flip flop, Low power, Pulse triggered, Cadence.
The present research paper proposes to implement a low power pulse-triggered flip-flop. The proposed design is MHLFF (modified hybrid latch flip-flop). In MHLFF method, the pulse generator will be altered concerning illustration inverters whatâ€™s more a pasquinade transistor. This technique will be comparative should understood kind about flip flop whatâ€™s more it utilizes a static lock structure. Should succeed Most exceedingly bad situation delay issue brought on Eventually Tom's perusing discharging way comprise from claiming three stacked transistor MHLFF may be presented. We can minimize the power and delay when compared to the existing models i.e, CDFF and SCDFF. The circuit was implementing using Cadence Virtuoso tool in 90-nm and 45-nm technology.
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