Implementation of MHLFF based low power pulse triggered flip flop

  • Authors

    • Shreya Verma
    • Tunikipati Usharani
    • S Iswariya
    • Bhavana Godavarthi
  • Flip flop, Low power, Pulse triggered, Cadence.
  • The present research paper proposes to implement a low power pulse-triggered flip-flop. The proposed design is MHLFF (modified hybrid latch flip-flop). In MHLFF method, the pulse generator will be altered concerning illustration inverters what’s more a pasquinade transistor. This technique will be comparative should understood kind about flip flop what’s more it utilizes a static lock structure. Should succeed Most exceedingly bad situation delay issue brought on Eventually Tom's perusing discharging way comprise from claiming three stacked transistor MHLFF may be presented.  We can minimize the power and delay when compared to the existing models i.e, CDFF and SCDFF. The circuit was implementing using Cadence Virtuoso tool in 90-nm and 45-nm technology.

  • References

    1. [1]. Dekker, Cees; Tans, Sander J.; Verschueren, Alwin R. M. (1998). "Room-temperature transistor based on a single carbon nano tube". Nature. 393 (6680): 49–52. International Technology Roadmap for Semiconductors Archived August 25, 2011, at the Wayback Machine. 2009 Edition

      [2]. H. Kawaguchi and T. Sakurai, “A reduced clock-swing flip-flop (RCSFF) for 63% power reduction,†IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 807–811, May 1998

      [3]. K. Chen, “A 77% energy saving 22-transistor single phase clocking D-flip-flop with adoptive-coupling configuration in 40 nm CMOS,†in Proc. IEEE Int. Solid-State Circuits Conf., Nov. 2011, pp. 338–339

      [4]. E. Consoli, M. Alioto, G. Palumbo, and J. Rabaey, “Conditional push-pull pulsed latch with 726 fJops energy delay product in 65 nm CMOS,†in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2012, pp. 482–483.

      [5]. P. Zhao, T. Darwish, and M. Bayoumi, “High-performance and low power conditional discharge flip-flop,†IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 477–484, May 2004.

      [6]. M.-W. Phyu, W.-L. Goh, and K.-S. Yeo, “A low-power static dual edge triggered flip-flop using an output-controlled discharge configura-tion,†in Proc. IEEE Int. Symp. Circuits Syst., May 2005, pp. 2429–2432.

      [7]. S. H. Rasouli, A. Khademzadeh, A. Afzali-Kusha, and M. Nourani, “Low power single- and double-edge-triggered flip-flops for high speed applications,†IEE Proc. Circuits Devices Syst., vol. 152, no. 2, pp. 118–122, Apr. 2005.

      [8]. S. Sadrossadat, H. Mostafa, and M. Anis, “Statistical design framework of sub-micron flip-flop circuits considering die-to-die and within-die variations,†IEEE Trans. Semicond. Manuf., vol. 24, no. 2, pp. 69–79, Feb. 2011.

      [9]. M. Alioto, E. Consoli, and G. Palumbo, “Flip-flop energy/performance versus Clock Slope and impact on the clock network design,†IEEE Trans. Circuits Syst., vol. 57, no. 6, pp. 1273–1286, Jun. 2010

      [10]. Ummadisetty Nagamani, Vydehi Merusomayajula, G Divya, Paparao Nalajala, Bhavana Godavarthi,†Design of fault tolerant alu using triple modular redundancy and clock gatingâ€, Journal of Advanced Research in Dynamical and Control Systems Vol. 9. Sp– 17 / 2017

      [11]. C Devi Supraja, E Vijaya Babu2, Rohith Bala Jaswanth B, Paparao Nalajala, Bhavana Godavarthi,â€Design and analysis of cnfet based 2:1 mux in nano scale regionâ€, Journal of Advanced Research in Dynamical and Control Systems Vol. 9. Sp– 18 / 2017

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  • How to Cite

    Verma, S., Usharani, T., Iswariya, S., & Godavarthi, B. (2017). Implementation of MHLFF based low power pulse triggered flip flop. International Journal of Engineering & Technology, 7(1.1), 483-485.